Index: devs/eth/powerpc/quicc/current/ChangeLog =================================================================== RCS file: /home/cvs/ecc/ecc/devs/eth/powerpc/quicc/current/ChangeLog,v retrieving revision 1.9 diff -u -5 -p -r1.9 ChangeLog --- devs/eth/powerpc/quicc/current/ChangeLog 2001/01/30 19:04:09 1.9 +++ devs/eth/powerpc/quicc/current/ChangeLog 2001/05/07 16:23:30 @@ -1,5 +1,9 @@ +2001-05-07 Gary Thomas + + * src/if_quicc.c (quicc_eth_init): Get ESA from RedBoot 'fconfig' data. + 2001-01-30 Gary Thomas * src/if_quicc.c: New RedBoot config data layout. 2001-01-03 Gary Thomas Index: devs/eth/powerpc/quicc/current/src/if_quicc.c =================================================================== RCS file: /home/cvs/ecc/ecc/devs/eth/powerpc/quicc/current/src/if_quicc.c,v retrieving revision 1.7 diff -u -5 -p -r1.7 if_quicc.c --- devs/eth/powerpc/quicc/current/src/if_quicc.c 2001/01/30 19:04:09 1.7 +++ devs/eth/powerpc/quicc/current/src/if_quicc.c 2001/05/07 15:59:06 @@ -78,11 +78,12 @@ static unsigned char quicc_eth_rxbufs[CY [CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE]; static unsigned char quicc_eth_txbufs[CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM] [CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE]; static struct quicc_eth_info quicc_eth0_info; -static unsigned char enaddr[] = { 0x08, 0x00, 0x3E, 0x28, 0x79, 0xB8}; +static unsigned char _default_enaddr[] = { 0x08, 0x00, 0x3E, 0x28, 0x79, 0xB8}; +static unsigned char enaddr[6]; #ifdef CYGPKG_REDBOOT #include #ifdef CYGSEM_REDBOOT_FLASH_CONFIG #include #include @@ -92,10 +93,16 @@ RedBoot_config_option("Network hardware CONFIG_ESA, 0 ); #endif #endif +// For fetching the ESA from RedBoot +#include +#ifndef CONFIG_ESA +#define CONFIG_ESA 6 +#endif + ETH_DRV_SC(quicc_eth0_sc, &quicc_eth0_info, // Driver specific data "eth0", // Name for this interface quicc_eth_start, quicc_eth_stop, @@ -160,15 +167,15 @@ quicc_eth_init(struct cyg_netdevtab_entr if (_mbx_fetch_VPD(VPD_ETHERNET_ADDRESS, enaddr, sizeof(enaddr)) == 0) { #if defined(CYGPKG_REDBOOT) && \ defined(CYGSEM_REDBOOT_FLASH_CONFIG) flash_get_config("quicc_esa", enaddr, CONFIG_ESA); #else - enet_pram = &eppc->pram[0].enet_scc; - ap = &enaddr[sizeof(enaddr)]; - ep = (unsigned char *)&enet_pram->paddr_h; - for (i = 0; i < sizeof(enaddr); i++) { - *ap++ = *--ep; + if (!CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET, + "quicc_esa", enaddr, CONFIG_ESA)) { + // Can't figure out ESA + diag_printf("QUICC_ETH - Warning! ESA unknown\n"); + memcpy(&enaddr, &_default_enaddr, sizeof(enaddr)); } #endif } // Ensure consistent state between cache and what the QUICC sees @@ -354,10 +361,11 @@ quicc_eth_init(struct cyg_netdevtab_entr static void quicc_eth_stop(struct eth_drv_sc *sc) { struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private; volatile struct scc_regs *scc = qi->ctl; + // Disable the device! scc->scc_gsmr_l &= ~(QUICC_SCC_GSML_ENR | QUICC_SCC_GSML_ENT); } // @@ -369,10 +377,11 @@ quicc_eth_stop(struct eth_drv_sc *sc) static void quicc_eth_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags) { struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private; volatile struct scc_regs *scc = qi->ctl; + // Enable the device! scc->scc_gsmr_l |= QUICC_SCC_GSML_ENR | QUICC_SCC_GSML_ENT; } // @@ -400,10 +409,11 @@ quicc_eth_control(struct eth_drv_sc *sc, static int quicc_eth_can_send(struct eth_drv_sc *sc) { struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private; volatile struct cp_bufdesc *txbd = qi->txbd; + return ((txbd->ctrl & QUICC_BD_CTL_Ready) == 0); } // // This routine is called to send data to the hardware. @@ -413,10 +423,11 @@ quicc_eth_send(struct eth_drv_sc *sc, st { struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private; volatile struct cp_bufdesc *txbd, *txfirst; volatile char *bp; int i, txindex, cache_state; + // Find a free buffer txbd = txfirst = qi->txbd; while (txbd->ctrl & QUICC_BD_CTL_Ready) { // This buffer is busy, move to next one if (txbd->ctrl & QUICC_BD_CTL_Wrap) { @@ -467,10 +478,11 @@ quicc_eth_send(struct eth_drv_sc *sc, st static void quicc_eth_RxEvent(struct eth_drv_sc *sc) { struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private; volatile struct cp_bufdesc *rxbd; + rxbd = qi->rnext; while ((rxbd->ctrl & (QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int)) == QUICC_BD_CTL_Int) { qi->rxbd = rxbd; // Save for callback (sc->funs->eth_drv->recv)(sc, rxbd->length); rxbd->ctrl |= QUICC_BD_CTL_Ready; @@ -495,10 +507,11 @@ static void quicc_eth_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len) { struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private; unsigned char *bp; int i, cache_state; + bp = (unsigned char *)qi->rxbd->buffer; // Note: the MBX860 does not seem to snoop/invalidate the data cache properly! HAL_DCACHE_IS_ENABLED(cache_state); if (cache_state) { HAL_DCACHE_INVALIDATE(qi->rxbd->buffer, qi->rxbd->length); // Make sure no stale data @@ -515,10 +528,11 @@ static void quicc_eth_TxEvent(struct eth_drv_sc *sc, int stat) { struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private; volatile struct cp_bufdesc *txbd; int txindex; + txbd = qi->tnext; while ((txbd->ctrl & (QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int)) == QUICC_BD_CTL_Int) { txindex = ((unsigned long)txbd - (unsigned long)qi->tbase) / sizeof(*txbd); txbd->ctrl &= ~QUICC_BD_CTL_Int; // Reset int pending bit (sc->funs->eth_drv->tx_done)(sc, qi->txkey[txindex], 0); @@ -539,10 +553,11 @@ static void quicc_eth_int(struct eth_drv_sc *sc) { struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private; volatile struct scc_regs *scc = qi->ctl; unsigned short scce; + while ((scce = (scc->scc_scce & QUICC_SCCE_INTS)) != 0) { if ((scce & (QUICC_SCCE_TXE | QUICC_SCCE_TX)) != 0) { quicc_eth_TxEvent(sc, scce); } if ((scce & QUICC_SCCE_RXF) != 0) { Index: hal/powerpc/mbx/.Sanitize =================================================================== RCS file: /home/cvs/ecc/ecc/hal/powerpc/mbx/.Sanitize,v retrieving revision 1.2 diff -u -5 -p -r1.2 .Sanitize --- hal/powerpc/mbx/.Sanitize 2000/02/14 17:18:05 1.2 +++ hal/powerpc/mbx/.Sanitize 2001/05/05 14:29:42 @@ -27,10 +27,11 @@ Do-first: # The lines between the "Do-last:" line and the file's end are executed # as a /bin/sh shell script after everything else is done in this script. # See the /usr/unsupported/bin/Sanitize script for more details. + Things-to-keep: current Things-to-lose: Index: hal/powerpc/mbx/current/ChangeLog =================================================================== RCS file: /home/cvs/ecc/ecc/hal/powerpc/mbx/current/ChangeLog,v retrieving revision 1.78 diff -u -5 -p -r1.78 ChangeLog --- hal/powerpc/mbx/current/ChangeLog 2001/05/05 14:46:40 1.78 +++ hal/powerpc/mbx/current/ChangeLog 2001/05/07 16:24:15 @@ -1,5 +1,11 @@ +2001-05-07 Gary Thomas + + * cdl/hal_powerpc_mbx.cdl: + Disable CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT_NOT_GUARANTEED since most + installations will now use RedBoot. + 2001-05-05 Gary Thomas * misc/redboot_ROM_40.ecm: * misc/redboot_RAM_40.ecm: New configuration - 40MHz boards. Index: hal/powerpc/mbx/current/cdl/hal_powerpc_mbx.cdl =================================================================== RCS file: /home/cvs/ecc/ecc/hal/powerpc/mbx/current/cdl/hal_powerpc_mbx.cdl,v retrieving revision 1.30 diff -u -5 -p -r1.30 hal_powerpc_mbx.cdl --- hal/powerpc/mbx/current/cdl/hal_powerpc_mbx.cdl 2001/05/05 14:46:40 1.30 +++ hal/powerpc/mbx/current/cdl/hal_powerpc_mbx.cdl 2001/05/07 16:06:41 @@ -53,11 +53,13 @@ cdl_package CYGPKG_HAL_POWERPC_MBX { compile hal_diag.c hal_aux.c mbx.S implements CYGINT_HAL_DEBUG_GDB_STUBS implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT - implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT_NOT_GUARANTEED + +# Note: uncomment this to get old-style debug behaviour +# implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT_NOT_GUARANTEED define_proc { puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H " puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H " Index: devs/eth/powerpc/quicc/current/ChangeLog =================================================================== RCS file: /home/cvs/ecc/ecc/devs/eth/powerpc/quicc/current/ChangeLog,v retrieving revision 1.10 diff -u -5 -p -r1.10 ChangeLog --- devs/eth/powerpc/quicc/current/ChangeLog 2001/05/07 16:26:10 1.10 +++ devs/eth/powerpc/quicc/current/ChangeLog 2001/05/07 21:00:39 @@ -1,8 +1,11 @@ 2001-05-07 Gary Thomas * src/if_quicc.c (quicc_eth_init): Get ESA from RedBoot 'fconfig' data. + Improve interrupt interroperability when running with RedBoot and + sharing the network connection. Proper operation requires a new + RedBoot at least as new as this file. 2001-01-30 Gary Thomas * src/if_quicc.c: New RedBoot config data layout. Index: devs/eth/powerpc/quicc/current/src/if_quicc.c =================================================================== RCS file: /home/cvs/ecc/ecc/devs/eth/powerpc/quicc/current/src/if_quicc.c,v retrieving revision 1.8 diff -u -5 -p -r1.8 if_quicc.c --- devs/eth/powerpc/quicc/current/src/if_quicc.c 2001/05/07 16:26:11 1.8 +++ devs/eth/powerpc/quicc/current/src/if_quicc.c 2001/05/07 22:09:31 @@ -119,30 +119,36 @@ NETDEVTAB_ENTRY(quicc_netdev, quicc_eth_init, &quicc_eth0_sc); extern int _mbx_fetch_VPD(int, void *, int); +#ifdef CYGPKG_NET static cyg_interrupt quicc_eth_interrupt; static cyg_handle_t quicc_eth_interrupt_handle; +#endif static void quicc_eth_int(struct eth_drv_sc *data); +#ifdef CYGPKG_NET // This ISR is called when the ethernet interrupt occurs static int quicc_eth_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs) { cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_CPM_SCC1); + cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_CPM_SCC1); return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Run the DSR } +#endif // Deliver function (ex-DSR) handles the ethernet [logical] processing static void quicc_eth_deliver(struct eth_drv_sc * sc) { quicc_eth_int(sc); +#ifdef CYGPKG_NET // Allow interrupts to happen again - cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_CPM_SCC1); cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_CPM_SCC1); +#endif } // // Initialize the interface - performed at system startup // This function must set up the interface, including arranging to @@ -159,32 +165,35 @@ quicc_eth_init(struct cyg_netdevtab_entr volatile struct ethernet_pram *enet_pram; volatile struct scc_regs *scc; int TxBD, RxBD; int cache_state; int i; + bool esa_ok; // Fetch the board address from the VPD #define VPD_ETHERNET_ADDRESS 0x08 if (_mbx_fetch_VPD(VPD_ETHERNET_ADDRESS, enaddr, sizeof(enaddr)) == 0) { #if defined(CYGPKG_REDBOOT) && \ defined(CYGSEM_REDBOOT_FLASH_CONFIG) - flash_get_config("quicc_esa", enaddr, CONFIG_ESA); + esa_ok = flash_get_config("quicc_esa", enaddr, CONFIG_ESA); #else - if (!CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET, - "quicc_esa", enaddr, CONFIG_ESA)) { + esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET, + "quicc_esa", enaddr, CONFIG_ESA); +#endif + if (!esa_ok) { // Can't figure out ESA diag_printf("QUICC_ETH - Warning! ESA unknown\n"); memcpy(&enaddr, &_default_enaddr, sizeof(enaddr)); } -#endif } // Ensure consistent state between cache and what the QUICC sees HAL_DCACHE_IS_ENABLED(cache_state); HAL_DCACHE_SYNC(); HAL_DCACHE_DISABLE(); +#ifdef CYGPKG_NET // Set up to handle interrupts cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_CPM_SCC1, CYGARC_SIU_PRIORITY_HIGH, (cyg_addrword_t)sc, // Data item passed to interrupt handler (cyg_ISR_t *)quicc_eth_isr, @@ -192,10 +201,11 @@ quicc_eth_init(struct cyg_netdevtab_entr &quicc_eth_interrupt_handle, &quicc_eth_interrupt); cyg_drv_interrupt_attach(quicc_eth_interrupt_handle); cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_CPM_SCC1); cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_CPM_SCC1); +#endif qi->pram = enet_pram = &eppc->pram[0].enet_scc; qi->ctl = scc = &eppc->scc_regs[0]; // Use SCC1 // Shut down ethernet, in case it is already running @@ -423,10 +433,11 @@ quicc_eth_send(struct eth_drv_sc *sc, st { struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private; volatile struct cp_bufdesc *txbd, *txfirst; volatile char *bp; int i, txindex, cache_state; + unsigned int ctrl; // Find a free buffer txbd = txfirst = qi->txbd; while (txbd->ctrl & QUICC_BD_CTL_Ready) { // This buffer is busy, move to next one @@ -462,12 +473,16 @@ quicc_eth_send(struct eth_drv_sc *sc, st HAL_DCACHE_IS_ENABLED(cache_state); if (cache_state) { HAL_DCACHE_INVALIDATE(txbd->buffer, txbd->length); // Make sure no stale data } // Send it on it's way - txbd->ctrl |= QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int | - QUICC_BD_TX_PAD | QUICC_BD_TX_LAST | QUICC_BD_TX_TC; + ctrl = txbd->ctrl & ~QUICC_BD_TX_PAD; + if (txbd->length < IEEE_8023_MIN_FRAME) { + ctrl |= QUICC_BD_TX_PAD; + } + txbd->ctrl = ctrl | QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int | + QUICC_BD_TX_LAST | QUICC_BD_TX_TC; } // // This function is called when a packet has been received. It's job is // to prepare to unload the packet from the hardware. Once the length of Index: hal/common/current/ChangeLog =================================================================== RCS file: /home/cvs/ecc/ecc/hal/common/current/ChangeLog,v retrieving revision 1.272 diff -u -5 -p -r1.272 ChangeLog --- hal/common/current/ChangeLog 2001/04/30 16:55:52 1.272 +++ hal/common/current/ChangeLog 2001/05/07 22:13:35 @@ -1,5 +1,11 @@ +2001-05-07 Gary Thomas + + * src/hal_if.c (hal_ctrlc_check): Only return 'true' if the ISR/DSR + actually processes a ^C. Otherwise, interrupts/date can be lost on + a shared channel (like an ethernet device). + 2001-04-30 Gary Thomas * cdl/hal.cdl: Add configury to control initial cache behaviour. 2001-04-30 Hugo Tyson Index: hal/common/current/src/hal_if.c =================================================================== RCS file: /home/cvs/ecc/ecc/hal/common/current/src/hal_if.c,v retrieving revision 1.35 diff -u -5 -p -r1.35 hal_if.c --- hal/common/current/src/hal_if.c 2001/03/21 14:41:56 1.35 +++ hal/common/current/src/hal_if.c 2001/05/07 22:11:25 @@ -766,13 +766,14 @@ hal_ctrlc_check(CYG_ADDRWORD vector, CYG (CYGACC_CALL_IF_VERSION() & CYGNUM_CALL_IF_TABLE_VERSION_CALL_MASK))){ gdb_vector = CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_DBG_ISR_VECTOR); } if (vector == gdb_vector) { isr_ret = CYGACC_COMM_IF_DBG_ISR(*__chan, &ctrlc, vector, data); - if (ctrlc) + if (ctrlc) { cyg_hal_user_break( (CYG_ADDRWORD *)hal_saved_interrupt_state ); - return true; + return true; + } } return false; } #endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT || CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT Index: redboot/current/ChangeLog =================================================================== RCS file: /home/cvs/ecc/ecc/redboot/current/ChangeLog,v retrieving revision 1.132 diff -u -5 -p -r1.132 ChangeLog --- redboot/current/ChangeLog 2001/04/26 13:56:59 1.132 +++ redboot/current/ChangeLog 2001/05/07 20:56:45 @@ -1,5 +1,10 @@ +2001-05-07 Gary Thomas + + * src/net/net_io.c (net_io_isr): Interrupt acknowledgement + should rightly be done by the driver 'delivery' routine, not here. + 2001-04-26 Gary Thomas * src/main.c (do_caches): Display cache state if no arguments. 2001-04-13 Gary Thomas Index: redboot/current/src/net/net_io.c =================================================================== RCS file: /home/cvs/ecc/ecc/redboot/current/src/net/net_io.c,v retrieving revision 1.24 diff -u -5 -p -r1.24 net_io.c --- redboot/current/src/net/net_io.c 2001/03/20 19:46:55 1.24 +++ redboot/current/src/net/net_io.c 2001/05/07 20:57:48 @@ -390,11 +390,10 @@ static int net_io_isr(void *__ch_data, int* __ctrlc, CYG_ADDRWORD __vector, CYG_ADDRWORD __data) { char ch; - cyg_drv_interrupt_acknowledge(__vector); *__ctrlc = 0; if (net_io_getc_nonblock(__ch_data, &ch)) { if (ch == 0x03) { *__ctrlc = 1; }