From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gary Thomas To: Jesper Skov Cc: ecos-discuss@sourceware.cygnus.com, Daniel Kahlin Subject: Re: [ECOS] ppc603e cache sync Date: Fri, 13 Aug 1999 18:03:00 -0000 Message-id: References: X-SW-Source: 1999-08/msg00015.html On 13-Aug-99 Jesper Skov wrote: >>>>>> "Daniel" == Daniel Kahlin writes: > >>> The only other place were we do this by steam is in the kcache >>> tests. There the array is called 'dca' - data cache array or some >>> such. Not something that has been blessed with official policy >>> (yet). > > Daniel> I will have to put and ifdef:ed array somewhere in the hal. > Daniel> maybe in arch/hal_misc.c. cyg_uint8 > Daniel> hal_data_cache_array[HAL_DCACHE_SIZE] > > Looks good to me. Remember to use GCC attributes to ensure proper > alignment. > >>> Doesn't it have the implementation specific flush-all command as >>> the 603? I don't have my manuals close by, unfortunately, but the >>> 603 definitely has a one-shot operation for flushing (or is it >>> clearing?) the cache. > > Daniel> You probably mean the DCFI bit in HID0. It invalidates the > Daniel> cache, and that would be fine, if it wasn't for the cache > Daniel> being writeback. But maybe I've missed something in the > Daniel> documentation. > > Yup, that's what I was thinking about. If there's only the DCFI bit, > that's probably all. Too bad. > There is no magic "flush and invalidate all entries" operation on any PowerPC I know about. The DCFI only invalidates, no flush. >>> If not, maybe something like the below would be better (from my >>> Linux/APUS sources): > > Daniel> The problem with using the 'dcbz' (and all other) cache > Daniel> instructions is that the operate on memory addresses instead > Daniel> of indexes into the cache. Normally that is what you want, > Daniel> but if you want to flush all cache entries into memory you > Daniel> would have to scan the entire 32 bit address range. Trick: > Daniel> Allocate all entries of the cache to an unused area. > This isn't strictly true. Given that each cache line has a tag which is comprised in part of only a few address bits, you can use 'dcbz' or 'dcbtst' as long as you cover a range of addresses which are sufficiently large to cause all lines in the cache to be touched. It's not necessary to actually access the address that's in the cache, only some address whose cache tag matches.