[ECOS] Configuration for at91sam7se-ek

[ECOS] Configuration for at91sam7se-ek

[Davies, Greg]

Hi,
    I've been using ecos on an at91sam7se-ek board, using the drivers
and template for the at91sam7s-ek board. It's been working okay until
today when it stopped working altogether. It's a problem I got around
once before, but my old configurations don't work anymore, and I don't
remember how I got it to work in the first place. 

When I force a break with the debugger the program is invariably on one
of the first three lines of wait_pmc_sr_2 in
cyg/hal/hal_platform_setup.h. I thought what got it working before was
setting the pll multiplier to 72 and the divider to 14, values that I
got from a sample project that comes with the eval kit, but these values
don't seem to work anymore. 

Does this problem sound familiar to anyone? If it doesn't does anyone
have a configuration file that works for the at91sam7se-ek board and the
at91sam7s-ek hal code that's currently in the repository?

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Re: [ECOS] Configuration for at91sam7se-ek

[Tom Deconinck]

Hi,

Yes, I'm using the same evaluation kit AT91SAM7SE-EK.
I took the AT91SAM7S-EK platform as a starting point and added a
AT91SAM7SE-EK specific platform. It's basically the same as the
AT91SAM7S-EK, with some addition and changes.
It looks like there is something wrong with your clock configurations,
I haven't seen such a problem myself.

These are the clock settings I'm using: (gotten them using configtool
on my ecc file)
CPU clock speed: 48000000
Main oscillator frequency: 18432000
Divider for PLL clock: 24
Multiplier for PLL clock: 125
Slow clock frequency: 32768


Tom

On Feb 6, 2008 10:02 PM, Davies, Greg <Greg.Davies@ultra-uems.com> wrote:
> Hi,
>     I've been using ecos on an at91sam7se-ek board, using the drivers
> and template for the at91sam7s-ek board. It's been working okay until
> today when it stopped working altogether. It's a problem I got around
> once before, but my old configurations don't work anymore, and I don't
> remember how I got it to work in the first place.
>
> When I force a break with the debugger the program is invariably on one
> of the first three lines of wait_pmc_sr_2 in
> cyg/hal/hal_platform_setup.h. I thought what got it working before was
> setting the pll multiplier to 72 and the divider to 14, values that I
> got from a sample project that comes with the eval kit, but these values
> don't seem to work anymore.
>
> Does this problem sound familiar to anyone? If it doesn't does anyone
> have a configuration file that works for the at91sam7se-ek board and the
> at91sam7s-ek hal code that's currently in the repository?
>
> --
> Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
> and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss
>
>

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[ECOS] Changing PLL register was: Configuration for at91sam7se-ek

[Davies, Greg]

So my problem was only partly to do with ecos, and had little to nothing
to do with the configuration. The problem was that the PLL settings in
the init section of my BDI2000 were different than the ones I had set in
eCos. That's where I got 72 and 14 in the first place, from the default
BDI configuration file. I have everything (BDI init section and ecos)
set to the default ecos template values of 24 for the divider and 125
for the multiplier. 

Something odd is happening in the Clock generator PLL register though. I
do a "reset halt" on the BDI, then check the membory af the PLL register
(0xFFFFFC2C). It shows the values that were set by the BDI from the init
section when I did the "reset halt" (divider:24, multiplier:125). When I
give it a "go" (like continue in gdb) and the a subsequent "halt" (like
a break in gdb) and check the register again, it's changed to values
similar to what I used to have there (divider:14, multiplier:71). I'm
not sure where it's getting these numbers, since I've reconfigured,
recompiled and reprogrammed the board with the new values for the pll
register in ecos. 

If no one has an answer for this, I don't mind, everything is working
fine (better than before). It just seems odd. 

-----Original Message-----
From: ecos-discuss-owner@ecos.sourceware.org
[mailto:ecos-discuss-owner@ecos.sourceware.org] On Behalf Of Davies,
Greg
Sent: Wednesday, February 06, 2008 5:03 PM
To: ecos-discuss@sources.redhat.com
Subject: [ECOS] Configuration for at91sam7se-ek

Hi,
    I've been using ecos on an at91sam7se-ek board, using the drivers
and template for the at91sam7s-ek board. It's been working okay until
today when it stopped working altogether. It's a problem I got around
once before, but my old configurations don't work anymore, and I don't
remember how I got it to work in the first place. 

When I force a break with the debugger the program is invariably on one
of the first three lines of wait_pmc_sr_2 in
cyg/hal/hal_platform_setup.h. I thought what got it working before was
setting the pll multiplier to 72 and the divider to 14, values that I
got from a sample project that comes with the eval kit, but these values
don't seem to work anymore. 

Does this problem sound familiar to anyone? If it doesn't does anyone
have a configuration file that works for the at91sam7se-ek board and the
at91sam7s-ek hal code that's currently in the repository?

--
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and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss


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RE: [ECOS] Changing PLL register was: Configuration for at91sam7se-ek

[Davies, Greg]

I've found the cause of all the strange problems I've had 
that I asked you guys for help with, and I want to share, 
mostly for newbies (like myself) to find in the archives. 
This includes all my issues in the "Changing flash wait state 
on SAM7" thread. 

The cause of all of it was that there was no PLL filter. They 
tell me that the code shouldn't have been able to run at all 
without it, but it did, and caused exactly the kinds of 
problems an erratic clock might cause. Thanks again to 
everyone who tried to help. 

Below is what I accepted as a solution at the time (it was working).

> -----Original Message-----
> From: ecos-discuss-owner@ecos.sourceware.org
> [mailto:ecos-discuss-owner@ecos.sourceware.org] On Behalf 
Of Davies, 
> Greg
> Sent: Thursday, February 07, 2008 3:52 PM
> To: ecos-discuss@sources.redhat.com
> Subject: [ECOS] Changing PLL register was: Configuration for 
> at91sam7se-ek
> 
> So my problem was only partly to do with ecos, and had little to 
> nothing to do with the configuration. The problem was that the PLL 
> settings in the init section of my BDI2000 were different than the 
> ones I had set in eCos. That's where I got
> 72 and 14 in the first place, from the default BDI 
configuration file. 
> I have everything (BDI init section and
> ecos) set to the default ecos template values of 24 for the divider 
> and 125 for the multiplier.
> 
> Something odd is happening in the Clock generator PLL 
register though. 
> I do a "reset halt" on the BDI, then check the membory af the PLL 
> register (0xFFFFFC2C). It shows the values that were set by the BDI 
> from the init section when I did the "reset halt" (divider:24, 
> multiplier:125). When I give it a "go" (like continue in 
gdb) and the 
> a subsequent "halt" (like a break in gdb) and check the register 
> again, it's changed to values similar to what I used to have there 
> (divider:14, multiplier:71). I'm not sure where it's getting these 
> numbers, since I've reconfigured, recompiled and reprogrammed the 
> board with the new values for the pll register in ecos.
> 
> If no one has an answer for this, I don't mind, everything 
is working 
> fine (better than before). It just seems odd.
> 
> -----Original Message-----
> From: ecos-discuss-owner@ecos.sourceware.org
> [mailto:ecos-discuss-owner@ecos.sourceware.org] On Behalf 
Of Davies, 
> Greg
> Sent: Wednesday, February 06, 2008 5:03 PM
> To: ecos-discuss@sources.redhat.com
> Subject: [ECOS] Configuration for at91sam7se-ek
> 
> Hi,
>     I've been using ecos on an at91sam7se-ek board, using 
the drivers 
> and template for the at91sam7s-ek board. It's been working 
okay until 
> today when it stopped working altogether.
> It's a problem I got around once before, but my old configurations 
> don't work anymore, and I don't remember how I got it to 
work in the 
> first place.
> 
> When I force a break with the debugger the program is invariably on 
> one of the first three lines of wait_pmc_sr_2 in 
> cyg/hal/hal_platform_setup.h. I thought what got it working 
before was 
> setting the pll multiplier to 72 and the divider to 14, 
values that I 
> got from a sample project that comes with the eval kit, but these 
> values don't seem to work anymore.
> 
> Does this problem sound familiar to anyone? If it doesn't 
does anyone 
> have a configuration file that works for the at91sam7se-ek 
board and 
> the at91sam7s-ek hal code that's currently in the repository?

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Re: [ECOS] Changing PLL register was: Configuration for at91sam7se-ek

[Andrew Lunn]

On Tue, Jun 17, 2008 at 08:50:50AM -0300, Davies, Greg wrote:
> I've found the cause of all the strange problems I've had 
> that I asked you guys for help with, and I want to share, 
> mostly for newbies (like myself) to find in the archives. 
> This includes all my issues in the "Changing flash wait state 
> on SAM7" thread. 
> 
> The cause of all of it was that there was no PLL filter.

Hi Greg

It is good to here you got your system working.

Im not really a HW engineer, so maybe this is a dumb question...

The Atmel document doc6112.pdf, which is the reference design of the
AT91SAM7S, where you missing the two capaciters to ground on either
side of the crystal? Or the resister/capacitor network to PLLRC? I
guess the second?

      Thanks
        Andrew

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RE: [ECOS] Changing PLL register was: Configuration for at91sam7se-ek

[Davies, Greg]

> Andrew Lunn
> Sent: Tuesday, June 17, 2008 10:20 AM
> To: Davies, Greg
> Cc: ecos discuss
> Subject: Re: [ECOS] Changing PLL register was: Configuration 
> for at91sam7se-ek
> > The cause of all of it was that there was no PLL filter.
> Im not really a HW engineer, so maybe this is a dumb question...
Neither am I, not by a long shot...

> The Atmel document doc6112.pdf, which is the reference design 
> of the AT91SAM7S, where you missing the two capaciters to 
> ground on either side of the crystal? Or the 
> resister/capacitor network to PLLRC? I guess the second?

It is the second. The electrical guy thought we were running straight
off the crystal, and I typically stop reading when the documentation
gets into hardware stuff, and the problem fit so nicely into that
disconnect. It also didn't help that it worked really well for a while,
and then stopped after a software change. 

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