[ECOS] eCos docs conflating Ethernt MII and MI interface?

[Grant Edwards <grante@visi.com>]

I've been looking at the doc page below:

 http://www.ecos.sourceware.org/docs-latest/ref/io-eth-phy-generic1.html

The page appears to be conflating the MII and MI interfaces to
a PHY.  Based on the data structure and some parts of the
description I think the page it talking about the two-wire,
half-duplex, bit-serial serial management interface (aka MI or
SMI).  

But, in other parts, it talks about the MII interface between
the MAC and the PHY. MII (media independant interface) is a
16-wire, nibble-wide, full-duplex interface that's used to
transfer Ethernet frames and control/status info between the
MAC and the PHY.

MII and MI are completely separate interfaces, and it's not
clear which interface this page is describing. At one point it
talks about using "set_data(), get_data(), set_clock(),
set_dir() are used to control the MII signals and run the
protocol." That must be referring to MI instead of MII.

IIRC, the same PHY registers are generally available via both
MII and MI.

It _could_ be that the bit_level_ops members are being used to
access the MI interface on the PHY directly via processor I/O
port pins and the reg_level_ops are being used to access the
PHY registers via the MAC (which in turn uses MII), but that's
not clear from the page.

-- 
Grant Edwards                   grante             Yow! Loni Anderson's hair
                                  at               should be LEGALIZED!!
                               visi.com            


-- 
Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss