[ECOS] Re: eCos docs conflating Ethernt MII and MI interface?

[Grant Edwards <grante@visi.com>]

On 2008-07-16, Andrew Lunn <andrew@lunn.ch> wrote:

> I always thought the SMI was a subpart of the MII.

Yes, you're right.  The documentation I'd been looking at for
one brand of PHYs documented them separately and gave the
impression that the nibble-wide bus also gave access to PHY
registers, but the nibble-wide path is for transmit and receive
data only.

> The PHY package provides two mechanisms for using the SMI. The
> package can do the bit banging of these two pins itself. Or it
> can make use of hardware bit-banging which many ethernet
> device provide. The PHY package hides these details so that
> the PHY driver does not have to care how it accesses the PHY
> registers.
>
>> IIRC, the same PHY registers are generally available via both
>> MII and MI.
>
> That is because they are one and the same...

I've been looking at some other MAC and PHY datasheets, and I
see that now.  I had misunderstood some PHY documentation and
believed (embarassingly, for many years now), that when you
accessed the PHY registers via the MAC, it was using the
nibble-wide path (which I referred to as MII) rather than the
serial MDC/MDIO interface.

> However, i agree, the text could be better.

It's mostly my bad due to my misconception that MII referred to
only the nibble-wide data paths.

-- 
Grant Edwards                   grante             Yow! Could I have a drug
                                  at               overdose?
                               visi.com            


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