Re: [ECOS]: several questions

Re: [ECOS]: several questions

[Nick Garnett]

张 亮 <johnsonest@hotmail.com> writes:

> Dear all,
>        I have several question about ecos2.0 on ARM achitecture:
>             1)It seemed that all threads(including user threads)
> runing in SVC mode.because ecos
>          init thread context' CPSR as SVC mode with interrupt
> enabled,when resume it, it        will run in SVC mode.I feel it is
> not reasnable, user may be destroy system mode.


eCos is for embedded use and is not a multi-user operating system. It
does not support memory protection and running in USR mode provides no
additional protection. It would simply make it harder to execute
privileged operations and would make the ARM HAL radically different
from all the other architectures we support.


>        2) handle_IRQ_or_FIQ:
> 
>         mrs     r4,cpsr                 // switch to Supervisor Mode
>         bic     r4,r4,#CPSR_MODE_BITS
>         orr     r4,r4,#CPSR_SUPERVISOR_MODE
>         msr     cpsr,r4   /********here, enable interrupt! if at this
> point, new interrupt                          occurs, context
> destroyed,right?************************?/

Why do you believe that this enables interrupts? Only the CPU mode
field of the CPSR is changed here.

>        3)
> 
>         FUNC_START_ARM(hal_thread_load_context, r2)
>         ldr     fp,[r0]                 // get context to restore
>         mrs     r0,cpsr                 // disable IRQ's
>         orr     r0,r0,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
>         msr     cpsr,r0
>         ldr     r0,[fp,#armreg_cpsr]
>         msr     spsr,r0
>         ldmfd   fp,{r0-r10,fp,ip,sp,lr}
>        #ifdef __thumb__
>         mrs     r1,spsr                 // r1 is scratch
> // [r0 holds initial thread arg]
>         msr     cpsr,r1                 // hopefully no mode switch
> here!*****************if mode swtiched, system down!
> RIGHT?****************************/

What makes you think there would be a mode switch here? As we have
already established, eCos runs in SVC mode.

-- 
Nick Garnett                    eCos Kernel Architect
http://www.ecoscentric.com/     The eCos and RedBoot experts


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Re: [ECOS]: several questions

[Nick Garnett]

"johnsonest" <johnsonest@hotmail.com> writes:

> Nick,
>     thank you for your response!
>     however,I doubt that: 
> 
>     1 for more and more mcu support MMU, ecos on arm arch how to
>     support MMU? or unneccesary for ever?

Just because hardware exists does not mean that we have to support it.

eCos was not designed to support an MMU for protection between user
level address spaces. It would require a significant redesign and
essentially a total reimplementation of eCos to properly support
this.


>     2 does ecos on arm arch support nested interrupt ? where enable
>     interrupt again during a interrupt process?

If an ISR wants to re-enable interrupts while it works it can do so
and the HAL will handle it. By default ISRs do not do this and eCos
then handles interrupts sequentially. 

-- 
Nick Garnett                    eCos Kernel Architect
http://www.ecoscentric.com/     The eCos and RedBoot experts


-- 
Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss

Re: [ECOS]: several questions

[Nick Garnett]

"johnsonest" <johnsonest@hotmail.com> writes:

> 
> 1) in IRQ handling,I do not know keep vector for what use?

The vector number is passed to the ISR handler. It allows common
interrupt handlers to detect which interrupt is being delivered.


> 2) since all thread and majority of ISR/DSR handler run in SVC mode,
>    save svc_lr and svc_sp for what?

You would have to ask the authors of that code for details. Note that
RedBoot is used for running more than just eCos applications, and this
is probably part of that support.

> 3)why save all context when IRQ occurs to SVC stack? I feel os
> should save context to current thread stack when no nested
> interrupt; when nested interrupt, os save context to interrupt
> stack. design ecos like this for what advantage?

The thread state is stored on the thread stack and nested interrupts
are nested on the interrupt stack. This is necessary since any
interrupt can result in a context switch and the thread must be ready
for that to happen.

-- 
Nick Garnett                    eCos Kernel Architect
http://www.ecoscentric.com/     The eCos and RedBoot experts


-- 
Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss