* [ECOS] SH4 cache problem
@ 2001-02-27 7:47 Suzuki, RyosIII
2001-02-27 20:25 ` Suzuki, RyosIII
2001-02-28 2:08 ` Jesper Skov
0 siblings, 2 replies; 3+ messages in thread
From: Suzuki, RyosIII @ 2001-02-27 7:47 UTC (permalink / raw)
To: ecos-discuss
Hello,
I found another SH4 problems in current CVS tree about cache,
I know current eCos doesn't support SH4's cache.
However I think it is gdb_stub problem since I can run with cache
by using Hardware debugger.
please check following, and I hope this problems is fixed in near future.
Thank you,
--- sh/sh4/current/include/var_cache.h Sat Nov 4 06:17:47 2000
+++ /home/projects/SH/SH4/packages/hal/sh/sh4/current/include/var_cache.h
W
ed Feb 28 00:20:38 2001
@@ -125,14 +125,14 @@
//#define HAL_ICACHE_BURST_SIZE(_size_)
// Set the cache write mode
-#define HAL_ICACHE_WRITE_MODE( _mode_ ) \
+#define HAL_DCACHE_WRITE_MODE( _mode_ ) \
CYG_MACRO_START \
cyg_uint32 _m_; \
if (HAL_DCACHE_WRITETHRU_MODE == _mode_) \
_m_ = CYGARC_REG_CCR_WT; \
else \
_m_ = CYGARC_REG_CCR_CB; \
- cyg_hal_cache_write_mode(_m_); \
+ cyg_hal_dcache_write_mode(_m_); \
CYG_MACRO_END
#define HAL_DCACHE_WRITETHRU_MODE 0
--- sh/sh4/current/src/variant.S Tue Feb 20 02:50:47 2001
+++ /home/projects/SH/SH4/packages/hal/sh/sh4/current/src/variant.S Wed Feb
28 00:20:51 2001
@@ -73,7 +73,8 @@
mov.l $nCYGARC_REG_CCR,r1
mov.l @r1,r0
mov #CYGARC_REG_CCR_OCE,r2
- mov.l r2,@r1
+ or r2,r0
+ mov.l r0,@r1
nop
rts
nop
@@ -164,7 +165,8 @@
mov.l $nCYGARC_REG_CCR,r1
mov.l @r1,r0
mov.l $nCYGARC_REG_CCR_ICE,r2
- mov.l r2,@r1
+ or r2,r0
+ mov.l r0,@r1
nop
rts
nop
--
Suzuki,Ryouzaburou
ryos@atom-tc.or.jp
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [ECOS] SH4 cache problem
2001-02-27 7:47 [ECOS] SH4 cache problem Suzuki, RyosIII
@ 2001-02-27 20:25 ` Suzuki, RyosIII
2001-02-28 2:08 ` Jesper Skov
1 sibling, 0 replies; 3+ messages in thread
From: Suzuki, RyosIII @ 2001-02-27 20:25 UTC (permalink / raw)
To: ecos-discuss
At 00:41 +0900 2001.02.28, Suzuki,RyosIII wrote:
>Hello,
>
>I found another SH4 problems in current CVS tree about cache,
>I know current eCos doesn't support SH4's cache.
>However I think it is gdb_stub problem since I can run with cache
>by using Hardware debugger.
>please check following, and I hope this problems is fixed in near future.
>
>Thank you,
I found another cache problem,
following is my patch.
Thank you,
--- var_cache.h Sat Nov 4 06:17:47 2000
+++ /home/projects/SH/SH4/packages/hal/sh/sh4/current/include/var_cache.h
W
ed Feb 28 00:49:49 2001
@@ -191,10 +191,10 @@
externC void cyg_hal_icache_invalidate_all(void);
// Enable the cache
-#define HAL_ICACHE_ENABLE() cyg_hal_dcache_enable()
+#define HAL_ICACHE_ENABLE() cyg_hal_icache_enable()
// Disable the cache
-#define HAL_ICACHE_DISABLE() cyg_hal_dcache_disable()
+#define HAL_ICACHE_DISABLE() cyg_hal_icache_disable()
// Invalidate the entire cache
#define HAL_ICACHE_INVALIDATE_ALL() cyg_hal_icache_invalidate_all()
--
Suzuki,Ryouzaburou
ryos@atom-tc.or.jp
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [ECOS] SH4 cache problem
2001-02-27 7:47 [ECOS] SH4 cache problem Suzuki, RyosIII
2001-02-27 20:25 ` Suzuki, RyosIII
@ 2001-02-28 2:08 ` Jesper Skov
1 sibling, 0 replies; 3+ messages in thread
From: Jesper Skov @ 2001-02-28 2:08 UTC (permalink / raw)
To: Suzuki, RyosIII; +Cc: ecos-discuss
>>>>> "Suzuki,RyosIII" == Suzuki,RyosIII <ryos@atom-tc.or.jp> writes:
Suzuki,RyosIII> Hello, I found another SH4 problems in current CVS
Suzuki,RyosIII> tree about cache, I know current eCos doesn't support
Suzuki,RyosIII> SH4's cache. However I think it is gdb_stub problem
Suzuki,RyosIII> since I can run with cache by using Hardware debugger.
Suzuki,RyosIII> please check following, and I hope this problems is
Suzuki,RyosIII> fixed in near future.
I've checked in the below.
Thanks!
Jesper
Index: sh3/current/ChangeLog
===================================================================
RCS file: /home/cvs/ecc/ecc/hal/sh/sh3/current/ChangeLog,v
retrieving revision 1.14
diff -u -5 -r1.14 ChangeLog
--- sh3/current/ChangeLog 2001/02/26 10:43:28 1.14
+++ sh3/current/ChangeLog 2001/02/28 10:07:49
@@ -1,5 +1,11 @@
+2001-02-28 Jesper Skov <jskov@redhat.com>
+
+ * src/variant.S (cyg_hal_cache_enable): Write ORed value, not just
+ the enable bit.
+ Problem noticed by Ryouzaburou Suzuki <ryos@atom-tc.or.jp>
+
2001-02-26 Jesper Skov <jskov@redhat.com>
* include/mod_regs_ser.h: Add a couple of zeroes to
SCIF clear masks (for looks - no semantic change).
Index: sh3/current/src/variant.S
===================================================================
RCS file: /home/cvs/ecc/ecc/hal/sh/sh3/current/src/variant.S,v
retrieving revision 1.3
diff -u -5 -r1.3 variant.S
--- sh3/current/src/variant.S 2001/01/18 10:42:08 1.3
+++ sh3/current/src/variant.S 2001/02/28 10:07:50
@@ -71,11 +71,12 @@
FUNC_START(cyg_hal_cache_enable)
GOTO_NONCACHED_SHADOW
mov #CYGARC_REG_CCR,r1
mov.l @r1,r0
mov #CYGARC_REG_CCR_CE,r2
- mov.l r2,@r1
+ or r2,r0
+ mov.l r0,@r1
nop
rts
nop
FUNC_START(cyg_hal_cache_disable)
Index: sh4/current/ChangeLog
===================================================================
RCS file: /home/cvs/ecc/ecc/hal/sh/sh4/current/ChangeLog,v
retrieving revision 1.10
diff -u -5 -r1.10 ChangeLog
--- sh4/current/ChangeLog 2001/02/26 10:43:28 1.10
+++ sh4/current/ChangeLog 2001/02/28 10:07:50
@@ -1,5 +1,13 @@
+2001-02-28 Jesper Skov <jskov@redhat.com>
+
+ * src/variant.S (cyg_hal_dcache_enable, cyg_hal_icache_enable):
+ Write ORed value, not just the enable bit.
+ * include/var_cache.h: Fix various macro typos.
+
+ Fixes from Ryouzaburou Suzuki <ryos@atom-tc.or.jp>
+
2001-02-26 Jesper Skov <jskov@redhat.com>
* include/mod_regs_ser.h: Add a couple of zeroes to SCIF clear
masks (for looks - no semantic change).
Index: sh4/current/include/var_cache.h
===================================================================
RCS file: /home/cvs/ecc/ecc/hal/sh/sh4/current/include/var_cache.h,v
retrieving revision 1.1
diff -u -5 -r1.1 var_cache.h
--- sh4/current/include/var_cache.h 2000/11/01 10:00:38 1.1
+++ sh4/current/include/var_cache.h 2001/02/28 10:07:50
@@ -123,18 +123,18 @@
// Set the cache refill burst size
//#define HAL_ICACHE_BURST_SIZE(_size_)
// Set the cache write mode
-#define HAL_ICACHE_WRITE_MODE( _mode_ ) \
+#define HAL_DCACHE_WRITE_MODE( _mode_ ) \
CYG_MACRO_START \
cyg_uint32 _m_; \
if (HAL_DCACHE_WRITETHRU_MODE == _mode_) \
_m_ = CYGARC_REG_CCR_WT; \
else \
_m_ = CYGARC_REG_CCR_CB; \
- cyg_hal_cache_write_mode(_m_); \
+ cyg_hal_dcache_write_mode(_m_); \
CYG_MACRO_END
#define HAL_DCACHE_WRITETHRU_MODE 0
#define HAL_DCACHE_WRITEBACK_MODE 1
@@ -189,14 +189,14 @@
externC void cyg_hal_icache_enable(void);
externC void cyg_hal_icache_disable(void);
externC void cyg_hal_icache_invalidate_all(void);
// Enable the cache
-#define HAL_ICACHE_ENABLE() cyg_hal_dcache_enable()
+#define HAL_ICACHE_ENABLE() cyg_hal_icache_enable()
// Disable the cache
-#define HAL_ICACHE_DISABLE() cyg_hal_dcache_disable()
+#define HAL_ICACHE_DISABLE() cyg_hal_icache_disable()
// Invalidate the entire cache
#define HAL_ICACHE_INVALIDATE_ALL() cyg_hal_icache_invalidate_all()
// Synchronize the contents of the cache with memory.
Index: sh4/current/src/variant.S
===================================================================
RCS file: /home/cvs/ecc/ecc/hal/sh/sh4/current/src/variant.S,v
retrieving revision 1.3
diff -u -5 -r1.3 variant.S
--- sh4/current/src/variant.S 2001/01/18 10:42:08 1.3
+++ sh4/current/src/variant.S 2001/02/28 10:07:50
@@ -71,11 +71,12 @@
FUNC_START(cyg_hal_dcache_enable)
GOTO_NONCACHED_SHADOW
mov.l $nCYGARC_REG_CCR,r1
mov.l @r1,r0
mov #CYGARC_REG_CCR_OCE,r2
- mov.l r2,@r1
+ or r2,r0
+ mov.l r0,@r1
nop
rts
nop
FUNC_START(cyg_hal_dcache_disable)
@@ -162,11 +163,12 @@
FUNC_START(cyg_hal_icache_enable)
GOTO_NONCACHED_SHADOW
mov.l $nCYGARC_REG_CCR,r1
mov.l @r1,r0
mov.l $nCYGARC_REG_CCR_ICE,r2
- mov.l r2,@r1
+ or r2,r0
+ mov.l r0,@r1
nop
rts
nop
FUNC_START(cyg_hal_icache_disable)
^ permalink raw reply [flat|nested] 3+ messages in thread
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2001-02-27 20:25 ` Suzuki, RyosIII
2001-02-28 2:08 ` Jesper Skov
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