From: Bart Veer <bartv@ecoscentric.com>
To: Iris Lindner <ilindner@logopak.de>
Cc: ecos-discuss@ecos.sourceware.org
Subject: Re: [ECOS] FLASH API v.2 and interrupts
Date: Thu, 08 Oct 2009 13:50:00 -0000 [thread overview]
Message-ID: <pnr5tet2og.fsf@delenn.bartv.net> (raw)
In-Reply-To: <200910081324.03408.ilindner@logopak.de> (message from Iris Lindner on Thu, 8 Oct 2009 13:24:02 +0200)
>>>>> "Iris" == Iris Lindner <ilindner@logopak.de> writes:
Iris> Dear Stanislav, dear Bart, dear Paul,
Iris> thank you very much for your detailed and helpful response!
<snip>
>> On other hardware the flash driver has to disable the cache
>> before it can talk directly to the flash chip. You do not want
>> interrupts or context switches while the cache is disabled, the
>> resulting system performance would be terrible. The
>> LEAVE_INTERRUPTS_ENABLED option is not available on hardware
>> like this.
Iris> I couldn't find disabling of cache in sources or chip
Iris> documentation.
http://ecos.sourceware.org/docs-latest/ref/am29xxxxx-instance.html
Then scroll down to the bottom, the last section describes Cache
Management. In the current sources look at am29xxxxx.c, especially
line 260 onwards.
>> So, switching to the V2 API would prevent the crashes. It would
>> no longer be necessary to disable interrupts in your own code,
>> instead that happens in the driver. However, a switch would not
>> address the performance problems unless the hardware supports
>> LEAVE_INTERRUPTS_ENABLED and you can guarantee that its
>> requirements are satisfied.
>>
>> There is a more advanced version of the AMD V2 driver which
>> disables interrupts for shorter periods of time. Writes happen
>> in burst with interrupts briefly reenabled between bursts.
>> Similarly erases happen in bursts, using the erase
>> suspend/resume facilities available in most NOR chips.
>> Interrupt latency is much improved but still not great - if the
>> erase bursts are too short then the chip may never make any
>> progress. The details vary between flash chips. This more
>> advanced driver is currently only available from eCosCentric.
Iris> So I think I could try to use the driver with interrupts
Iris> left enabled and making sure that flash is not accessed from
Iris> somewhere else, right? But when the machine is running it is
Iris> absolutely necessary to keep the can bus working. Anything
Iris> which has to do with flash (transferring a new file e.g.) is
Iris> of lower priority, so your last proposition of the advanced
Iris> AMD V2 driver sounds like a good solution, especially with
Iris> using suspend/resume functionality. (Does one have to
Iris> purchase it from eCosCentric?)
Yes. http://www.ecoscentric.com/cgi/info.cgi, or email
info@ecoscentric.com
Bart
--
Bart Veer eCos Configuration Architect
eCosCentric Limited The eCos experts http://www.ecoscentric.com/
Barnwell House, Barnwell Drive, Cambridge, UK. Tel: +44 1223 245571
Registered in England and Wales: Reg No 4422071.
>>>> Visit us at ESC-UK http://www.embedded.co.uk <<<<
>>>> Oct 7-8 on Stand 433 at FIVE ISC, Farnborough <<<<
--
Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss
prev parent reply other threads:[~2009-10-08 13:50 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-10-02 10:35 Iris Lindner
2009-10-02 10:50 ` [ECOS] IDE failed to identify unit 0 - wrote: a0, read: 7f Jim Bradleigh
2009-10-02 14:06 ` [ECOS] Debugging Redboot Jim Bradleigh
2009-10-07 16:20 ` Bart Veer
2009-10-02 11:13 ` [ECOS] FLASH API v.2 and interrupts Stanislav Meduna
2009-10-07 16:55 ` Bart Veer
2009-10-07 17:30 ` Paul D. DeRocco
2009-10-07 18:46 ` Bart Veer
2009-10-08 11:22 ` Iris Lindner
2009-10-08 13:50 ` Bart Veer [this message]
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