From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 24005 invoked by alias); 7 Jun 2004 14:27:20 -0000 Mailing-List: contact ecos-maintainers-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Post: List-Help: , Sender: ecos-maintainers-owner@sources.redhat.com Received: (qmail 23993 invoked from network); 7 Jun 2004 14:27:17 -0000 Message-ID: <012c01c44c9b$d68f1680$0b0110ac@ipitec.it> From: "Andrea Michelotti" To: "Jonathan Larmour" , "Gary Thomas" Cc: Subject: jtst (based on diopsis chip) new AT91 platform Date: Mon, 07 Jun 2004 14:27:00 -0000 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_010F_01C44CAC.1B893800" X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2800.1409 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1409 X-SW-Source: 2004-06/txt/msg00008.txt.bz2 This is a multi-part message in MIME format. ------=_NextPart_000_010F_01C44CAC.1B893800 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-length: 717 Hi, I've followed your suggestions I modified my diopsis ecos target and now it's nothing more that a new AT91 platform. I think some common improvements can be added regarding interrupt handling. I stripped all the dsp code, because I must understand which is the best way to integrate it or distribute it as a separate library (any suggestion is welcome). I tested redboot and all the ecos kernel tests. It works fine on my jtst board. I attached the diff between my modifications and ecos cvs repository (anonymous). The jtst.tar.gz contains the new platform directory: jtst. Please let me know if there's any changes to be done. thank you. Andrea. --------------------------- Andrea Michelotti - ATMEL Roma - ------=_NextPart_000_010F_01C44CAC.1B893800 Content-Type: application/octet-stream; name="jtst.tar.gz" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="jtst.tar.gz" Content-length: 9045 H4sIAMNwxEAAA+w9bXvaxrL5Wn7F1r73PtCDsSTeHLvJuTLGNq15KeAmOW0f PbJYbDVC4kjCiZvmv5+ZXUlIQiCwMWlPtIkFaGdmZ3dmZ2ZHL/u767iHL563 CEJFqFer8CkI9Zr/WWGfXnkhCkK1XpOkar38QhAlsSq+INVn5ouVmeOqNiEv Jrp2Rw1rKZxzrxuz6XQ5wN+z/I7y12a2Tc1n04M15V8ThbogIZxYrklCJv9d lIj8tZHxHDqwvvxrdVGQQP6VcrWeyX8XZUH+d6qhqPZEUd2XooK1JTj7tDYE FG6lskT+OOurTP6gJ3V2XhLKtfILImyni6vLVy7/ffJqCyW3n9snrCSqz7xa 7reJPHwpwqFal87qlYOzH8X8D8PBsEAu5SsyVbX36i0lmmWO9duZrbq6ZZKR 6qqMxnZ4xdJsdAcXvatGt/eu37q4HJ42L1odrIBq0rCmD7Z+e+eSfKNAxJcv j4p4fFkkEigsO4rsKJE+HZFL1S2SlqmVFnEBpkw6uvaeXKi2SV2XfG/Cr9v/ 11RDv1ftkmZNXud4q7RhOUR3yNimlDjW2P2g2vSEPFgzoqkmselId1xbv5m5 lOguUc3RoWWTiTXSxw94YmaOqI2E3DtKXGpPHGKN2Y+LzjW5oCa1VYP0ZjeG rpErXaOmQ4nqkCmece6gIzcPDPwcGEA6A48Hcm4BbSaKE0J1ALHJPbUdFI1E gIe86iKbNrGmCFQA3h6IobpzuFKsj/OujIhuslbvrCmwfQekoC8fdMMgN5TM HDqeGUUCkORNa3jZvR4SufMOSb2R+325M3x3AsDunQUA9J5yUvpkauhAGZi3 VdN9wHFoN/uNS4CXT1tXreE7YBuJnLeGneZgQM67fSKTntwfthrXV3Kf9K77 ve6gWSJkQGnKICKhMRMFjNWIuqpuOH6H34H0HODOGMHUuKcgRY3q98CbCjo+ fVhHQoZl3iIp7CYbwBOij4lpgdJ9sHVQBtcKxJYkM66bRSRRfUmGFAaHkp6h arRIBjMkUC6DUp9ajovAbZkIkiiKB2JZqJPrgex3RXaAaWdKNR2YpB81OuXU gRmL6cRYNyhI1wSLarq6ipxhY/DFQS0BWZKJqtmWg9TghG4auknJeGZqSAk1 35pAV3AOAKkiwjDttyZT+D2vQd0ngPseVCUYGc7DB8t+7+CITG1rNNMAlJ0i N6oDg26ZYfJzeiMLWIQRRWI3OJkcaoxh1iHLOLQ2dWaGq5u3nBiQv0EbBco9 nzWLIkRqnhRL5NL6APppM1AH5oqGBEaUKc6ckQm4I+K4nvZPVABQ70Gf1BuD qRnMFVXTLHukmkCA9duhbPRIvlxI1yZflkNsMZBh0H+gfw+GaYSywznMx9Sm qoPi+XD3EB9Obm4C7pndW2do4vzIBhgLE9QVpojBqxw2NMxgTNQHpMpm8y0n Cw7CVTUmkgUTDCbkznWnx4eHfKCdEvAChgWN7SHVLIcdDrx2DhHlYP2S7D+a nTPuPbboo/bPmoNGv9UbtrqdkH+CNuQZWDw77xSOuVtVvejFdfUcuiCTG1fL dhDgFoAnqgMK/96ihkHtImFOCEDPQNIeDVbAX1UOhNpBGZuJsRB0cVudzEFo oPgev/HuovfjhQJBgAJBgoJBgoJxAfmUQ8bAYYAlefDY3JPdCTWCIEIA0w+q dWOp9ojMo4k9hjlVMbb1O5jQDKdPx2CLlDsKU85OiGLuGJRuasZsRJWRDiEj 0R5uMVzO8bjHHqHd9Yg5mq3zqQXM5vzGhzAXWJ/CoQ4YqnsdMLhlwBDTdolJ 6QjUGgyNPTMDfDYZgCZEA7EBwDCK5Ee6NXV0pxAajtJejqH7NpQX7JIy0R2t pPFqm/57poOV49WfcJgu3/QjwwQyJ3vI/R75nAuPGXRA86TExnvmOuR/jo9R uM6DAy7AH9W9fY6B1E+vzhj1ody/aA6VS0D8fvr+FuM+fwlSunu990iqP8v9 Fvh6JBunymT6BNK9K3kI0UIbaCeS9tTl0fRxuIF9pdVVLvdy34SR41gRdhq9 a2zs1z0gUB+etVu/7iWzsJLKaVfunzEqTL/y2JlCJFh/FNnm22FfRrI+tqdB iIiaaZk4RT2lazfb3f475Up+h9HeXLF8E7DXphBpYYAJwYE752ZsqPfgMdhi wT9nWgrnJzgDgbc2w5hkBGqehybZqA9AD4fXPabjfbm9VyD/ZHYmIlXFVid7 5DggFSnJpLptn1qclDVZRS2tLFILZqU/rjwWTxxU5eqsFRrY5YPLgiyQKjdn EJ+ptxOQ1F4ENWnck8eeNcTV44AFDHw6lO6WchlBXV90e8HUnBiusiDEkjHS X8PYk+WDnyrOVS0w2QaNrGhlZUlpwqP/OaC+gfwv15O+N6dRVDsS+eUzCfyO S4KsEsYWRH73rAK/i4mbH3Ofc0/I/0TyfxgRPEMCeKP8v1jB/G+1Usvyv7so i/KHtdKNZbkKqH2JapMttLE6/yuUQe6x638Q0daz/O8uCgtK1XuKtlnxk3ri SS5yHkK0CaZcEoE/fV4H2j+5Ejqa9f0UWUf5C6wgpxQsoFZR9GE+EVgRzaji ZV5mDrUVdoZ80P8Ayt4P3RxTmAr+z9W8+mHr9ml7rnv7hHXTpfZY1Z4wILlF QbFl6aeFle/eHjmJrI3xO72B1To/HQiS4PqTGR2vxpfaQYAZXbYTz2CtCc6X r2vinDV/HijnV/LgUmmeAq9L0ALm502tC9rqnMNiaE3gfvPstNsdLgH3KXY5 xyEoX1LzKLBz3WYD0ui2290OcDFs9vvXveEA453Gj8qg9a+mJ8WQNtTESiWB 2NnpxTJi8s9Npd3qtNrQXqMLFW+Hi2SFdJoeboSgRyimlauInTVPry8U+Ak8 Nq6uz5rQ2+vTQTIhMYHQoMmH7XrQVCAYVIC11rDbX8JJiJfIuhZX96fXLTj6 Al0YkqTGu72hj6CctwarxjHSHDId4DFdhtE8b12sJ4gFZhW89AKL+GZjGYEv 7cay8siyIv7r7ir+k+rSQvxXFrL4bxcli/+y+C+L/7L4L4v/UuK/1Njv+YLH SFJyYSiB7lcZc35pz/nfUVbGf1tKAT4i/qvXs/hvJyWL/7L4L4v/svgvi/82 jv9S4qgdxX7go7/K8C+L/7ZSIvGfd3vjtm8B2Pz5r6pUyZ7/20lJlL9/G8qW 2thc/rVaLXv+bydlpfyX3jy3WRu4/lshf6leK3vyF6tVAeqlchXAsvXfDsrh ofeIReTGvwPSBr/8w8wgUpmI4nHl5bFQYY+95XKAwZ4e0fFxoFv2VAfeoMdu 7jsgI4s9R0JHupvL7XsKRb7HW+Uh5LHVQ/imuA9TWoK617kcv/0vx328A+pF jkm337podcgrIhTJVbNzMbzE7x+PQFf4zeoxqI81fHY0ClwRfGhV1+6p5kYx zs/PhaMoBmoix5iot7oWha+IQrQFsFOVH3Ofc7lBs4EPRwy8Lvg/FfbARviU MtY/YrwHvFi2Q/LY2SKQlpBsW1aaPyk/t+VCBMW2JnMEDz7o7BIcl350PWD5 qnXRIXlgv7Acfqyb+ibwtoW3fW6OIW7G1MfZdBOEW01T+PNMiosPS22Cu2l/ bhxnHXCM3q/k0yYuQs47eQVvkZ+KBVCeAO2ocBLVmmbnjJ0ohbSOg5QmyKbi fAxjg5J++i5f6glwvvCZvOaqG9wiGiElHgWkTq/Pz5v9ZFpBXYxe6W07GYGd /26h9XDb0kI3Rku6MXpENxJpBXVP7Ea09ZehjvQws5AsDl4Tb5mTkOMkkoeC 16SwUw7RmtrW7ZyQKHiU8HQp3K3Y3cKb+v/g1vYNfEyK/xcrtaqX/y1DCFAH /1+BL5n/30X5G/l/cXP//yX8c1UQMv/83+yfn/S8xV+tbG7/S3ebtpFm/2vV mm//hUqthus/8GyZ/d9FWWb/34BJl6c2GH8iltH+V6uPsf9jc0THRFHkwaDZ Pr2CiExZ7RXuXofqHXcE6Hgut0/NkT7OhR6YbbOE8wUzYOAQYLYyLyAIheVQ /CJH3nMPqwDl4bDPnggLncdzSp/8SRJOv1lKzOK8VVfzZs15O0oDXM5bYcmQ g8uhtkm0O1D1udnryG1oUFFs6lD7HnwfXoKb4PtbfvntZMmIBz4jhsOfnkuh WwDlWZNeMBpi4mikonlYjxgNzwukDwEDTOo3p7CUZ1Y9Z7TGdBGmTt7R/6CK W1jKU+EZHM8j7P+2839lqRzE/wL6ArD/NTHL/+2kPLP9f2L8/9G/PrB2InAB eJ4IREscga4mk95J2vDwcI2VyUKEumipGQu8IycsLZCOc7JiCWOFg+ajFTG2 t4qJwIvpqxhr41XMhhjiJij+KmZthIRVzCaNbbq8DC18guimSM67V1fdN63O BcmX4gwV/gqZyr9XonJ5qjLLVP6VMpVZeY7yuPwvVGzQRtr6X5Sk2Pq/Ui6L Wfy3i+LfxSvkbHqLX1gMJhAMhODj2655oN3pUzLA+8w8EITgIQfhaxeAy/mv IYy6OYGI7E/0vkns/xw6HH3MYfk/rwnvgwUc7DDHZj+BiQAV/1ikwQ5hpuBn HNALMbyPME/sRDL4/DOOICZwguEFP0YGCH7HYRcii4UTcwoLVXFijP9YrxL7 hPEB/s3B8Fccii90+XEOyX+DpuDNi8G/bzOj/bcqj7P/m6WA0+y/VK0H1//A GeD6v16TMvu/i/LM1/92k/91eAJ4Wc7UCWd+xRXJVWe7mV+eleYXJ79YUvqv nwH9sgnQr7w8Iv+7WfD/It3+lyv1+PW/WiWz/zspq+J/iOcEkUff34Zj/xW1 FtTykwLbKwHDx8euDbyIdb4gYBGm3+Zjw1bn3savidCSd0wPcoPQP34ZTPQ6 LYQ4D0Yk+BJe9oS/L1sYHUVYXbEUEkl0AfIVL4WE+VIoW5QsLY+4/3/r9n8x /1Ouidn+Pzspf+n8j8jzP2KW/8nyP1l5lvII+7/1+/9C+R/f/uOpzP7voHx1 +Z+jLP+T5X+y4pdE+4/72eBbSMYWGH/ddJ3NbX64pO3/Wa2L/vuf6tUyPv8j iln+ZzfFtw/45o9Ooxnd4qjVGQ6Uy/AsXgpzeLiNLcG8jcEOD9HLsJKgiuFq fO1OC19qZM+mbEtMohmW9p6ojqPfmrhXDd9GDvet4nhbZXP1TqLA5Cb7yvmO lXlS+Jyqtos7+qF/LrLdwZqTGzrCfcEa/vuXMPrvTtEF4054A763ClJ69Bam fHC3sxcpENrKXqRAZ6t7kUb7+NS9SIHU0/ciBSLb2YsUCC3uRco7vK29SIHU U/ciBRKP3IuUd2WLe5ECta3tReqPzFb2IgViW9yLFKhtcy9SIPf0vUi5LLe2 FykzN0/Zi9TTra3tRQrENt2LdGOfsWoz0mfwdsl7knoDF9mVNLwnKXNI4U1J vS1JsSK6BSn6pQOhfiBKWNeb2VPL8avPeBgy9/febpmMyvzFg8d8o019DoZ2 Yqxrjqfg3iacbH/MQz+4ILh5px9WBIVHPmAvQYV8/bh21Ns5x9HVLIQrSdHz 60XKpZJHzxvYhI1Wtx2vhOI4/2WAwYv7lLZ80WpcXg3nHAq51RjDFvgxIdwn cQ0EMYwgrYEghRHKqxHAQ/SHEZYqayBEWKquRhj0WhH6hNRSEcQoQj0FodX/ KdbEUTpGrI2X6RhSFEMU0lHKMZQUeSNKJYaSInFEqcZQyil6yDS3+TaMkiLE N/KwcXnWvQhhpEix1+qSGFspYmy+Hcb6LqXoIutHu3sWwkjpB7QRGywppR9g WoZv++GxkuopwwuNxNRRStFHwIipo5Sij4ARU8dyijoCRkwby2JyRwZ9fHso SSrJbSCC/DYRAdoAQ96x0GPRj64NMSg4OIfkhaJYwFBMvbf0EZlQWH5igIYx Eb+8RQDYdAwWBC9rtdG97gwTWs0ncPcPIha8XCz1m5g58zCnTyG+cfUJ5Qvi 1YPZHzZiTa4w+DlsdoMYZa2Fb5861C0FXEYyDP3moDnMF3IrakGvh/13+JCU yO+xyM2hz1s/gdaTT7/mIE5zMKyE9eorzLae/JpTnUl+b2Lzfa/to6IzdeyT vUJQ49jf4KmifcTPfgZmWY1l298APPzf/1/hZO94z97LqwUE8XKmBGOeFQmT L5348Up6/g8EM5s+KQGYkv8rC2LFf/9jpVLB9//BuUqW/9tFWZn/g5l13UtL APpAucPvthervlqRBfQUMlzf84N4P9T3lwYs4sckYV51HDq5MR7YSrew7dj6 VZYOzNKBWTowSwdm6cAsHfg1pANfbZ4RDOX8osnAWKYwkhAEl1Q5EGoHlYV0 IMvhTZc6fhvMLkxhZyE5uJDCS8ngeeHG612m6l59dxh/ewryda/aim5F75EJ 84z7N7G7ZXK5EjNnRFFca2TlCDFGNl/jCMVXuB0KZjTCp8Xiq9PWUBL/xKPE jmV2rLBjlR1r7FjHYxmQwU/6yL8A3X2frjLonvV/wwUQjB2fgzfgOJkBwbli fFAfHALxBpvDH3SHWTHqOs/GULcJ/JCAI4uAckxn7iqUXtPrgu+1cFrblvFY Hle11WDjxfgz6Ah8GdhYMGALLZWF6LkYx96gz5ybUPKb+THdDN7KAAAsI3BL 8abfBMVoXP140ezEGhdrHv/f+A3/FodY1kFODz+aHfn0qvlbjhWYdmM/vZ6P bXSi9OU2vpnEkxfrjAkGGu+oUp1wZh8M7XvmcpkqYSd9nrw+EVjp18djbaEK WFYUXPvB7FYYnQUQaQFEQeeCcM7sZg5XLgI1W0pqopTQhj9KHoe/2OJvCySF Iv4v4+1b3uqs1e4t2XEHN5gJZVBxM59cUmeDYQtYWextDMbv75LuJvR2sZGk 7gb3lfGPEnxM2O2CyzWi2y6QP/9cVc+UJtBzzwASbr+D03OVBX1XWqbutvmd j/PpgSchjtT/oP5dkd7UN7iGsTKx7h2vR1OtaDg22ZfCaVKkM8b9eYgn/yLp Ncj33mtsvXdMeYTovz2G8M9wDLIvSmFC+GopB9R8NAIzySJIw/qA99GDVXVW ELKRUKjnE13l9d8WP9nCgf0S4MQDW5Q+ew0N2QISIjXdHwK+wRdLnEHg7KSJ yJu3CUPNX+V1DiWox2nL66Ui/xOW41bFyKhZtr2A6ymTD+K4fn9Fv7+fQwLC /r7x1yjJAmafIF1bjCWnPfTGHcZ8gVycKVu33EBM+p5M9SlF05sL6djxXDlx 4QSfrGeCJJRFRpDtm5QIVAMgiQPhgxhJIPU5yMzEVHAi1NFaUC/XgpLXgrpZ C0pbC4onDPkwNNtyj3ib29Hl0DUGXfenMn+ExSnitIRFqD3CJcRiY8xzNU9b nqSbHz0PdDpz+PVntomeJ/kFbFEYh/XEV5APeBUZ1e332WSaE4XjVJOXPJ8i UyKikX2IojVcITFNOkTzg8GO9wxPWHPCrpsr2CIxuc0WU+T/ICoxIXpfRJY8 ZD45JeE4Wl1mgUJxvxKalKEqMVKlTaY+R/bcat2YbH9AsHY3iQNRFsaJU1bI ldn4cpuQC+JgT1Cew5nnNcPbvPFLCuBWB8oP1+1eABZNefJLXJ572acGOMql kF7zATvbvYDCcoUUg6BxcqY05YqEn8H90rnorOy+JD//Y4zZOnNLbaTs/1sF yz+//lPz9v/Knv/cSUm+/nOOW4ouu+7jVW4/mxRczvH1L3xufsvWPNeDztwB Z+xkl3OyyznZ5Zzsck52OSe7nJNdznmSw1v7co773qIsY/Ko6zm1hes5sjuh Rqqb3/hajh9L7Pb6DQznMy7ygvgoFKDJ/YbSu3w3aDVw0/uzM1jEDvLKR6UQ uhWuf91hN5myO+je9FvDpnLd6gzLUp7lO9oyEBk0/xH+oTTaZ8X4CQUIFU4C sv9p79p20waC6Hu+Yp8qW4BkYZsgQVFpoBXqhaogVX2qXC6JG4QlTJKHKP+e mVnb2NhQULlI9JwX4vXevNnLnNnZnR/t3nDwczDsflFyScCT5y9/yR3OBsXa yD4jOfLcEvD/jQz/CxejQ/v+Zuzv/9lx2P4P/p+Pj9z/f/LbsfRG8uhQZfyF /9fcmhWf/6661zbzf9vG/R8nwbHObae6UTqYTTE5NF7iI2ONRD7VQkD3vWMR xyIZTqId/CDUhVL7tbQUx1Zf/dG9+ugt5pPlUjXn9HT7bkSC96O3YCG1BY0A NALQCEAjAI0ANAJFi+Tu5703mndGL8rqT3gfPJYTxUFZyXKUUxHI4lax3Ipt 5ZQEIkBkZIecTkD1eJLhq188PbKpY65S+fHmfXg6fUDWmDO+XO/Om+mbzbZf h5bekZfdeA4PtxmHqjQoVWIju9KjcKNJw/ne7ZzmXh4U3U6oKjxkFtzbee7h OX0UzAIeTfL66Y6EZBEI9PI4liEY0DQw50Ul9GV6H68ypQH9MFFGXSyV5NDN lRyQvOJtarlVcDYZG3wij2KakSM8fvSpmwQNbc1VrKz41uuXMgaU2kea2ZBv 7rSH7dLN5/7NJ13zYKrNBHhYG1Tjt8qiiPRHU1ywMRr0WCqZqrGK6EfxfIpW 519+/xw3bWJNsEMFB1JBw6DPbLWM64pvmuqNnFc0m81qqtJc3f0zpoziTJKP 1hakGoWfXc9/9b7NXVDodLq9VOffS3XW2isp9IU9K3IHW/WvcLLkPhaud7JM B+TwBqc9rNKOR0e3/yHDhc7N99aR4/+iwTsp/3evq7VY/2M7VYv5v+vC/+tJ cCz+n+pG+/N/2QQA/wf/B/8H/wf/B/8H/0+Wmovj/+XIXKDIWmCLuQA0ARes CWCOtgOX42gbiJxknrNG4ATcog+Ug13lMyBLpqDjQD1nmOj3bruzm2mE5KF9 o79wq7BPeIPDiN4Xmk1I/Y7BMtMS97lZBQAAAAAAAAAAAAAAAAAAAAAAAHAu vAJI4Az/APAAAA== ------=_NextPart_000_010F_01C44CAC.1B893800 Content-Type: text/plain; name="jtstPatch.txt" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="jtstPatch.txt" Content-length: 12051 ? at572d740-dk2 ? jtst ? mypatch.txt Index: var/current/cdl/hal_arm_at91.cdl =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/cdl/hal_arm_at91= .cdl,v retrieving revision 1.6 diff -u -r1.6 hal_arm_at91.cdl --- var/current/cdl/hal_arm_at91.cdl 20 Feb 2004 18:45:04 -0000 1.6 +++ var/current/cdl/hal_arm_at91.cdl 7 Jun 2004 13:45:09 -0000 @@ -78,7 +78,7 @@ display "AT91 variant used" flavor data default_value {"R40807"} - legal_values {"R40807" "R40008" "M42800A" "M55800A" } + legal_values {"R40807" "R40008" "M42800A" "M55800A" "JTST" "JPMC= "} description "The AT91 microcontroller family has several varian= ts, the main differences being the amount of on-chip S= RAM, peripherals and their layout. This option allows t= he @@ -128,7 +128,7 @@ cdl_option CYGNUM_HAL_ARM_AT91_CLOCK_SPEED { display "CPU clock speed" flavor data - default_value {CYGHWR_HAL_ARM_AT91 =3D=3D "R40008" ? 66000000 : 32= 768000} + default_value {CYGHWR_HAL_ARM_AT91 =3D=3D "R40008" ? 66000000 : CY= GHWR_HAL_ARM_AT91 =3D=3D "JTST" || CYGHWR_HAL_ARM_AT91 =3D=3D "JPMC" ? 5000= 0000 : 32768000} } =20 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { @@ -164,7 +164,7 @@ display "Diagnostic serial port baud rate" flavor data legal_values 9600 19200 38400 57600 115200 - default_value 38400 + default_value {CYGHWR_HAL_ARM_AT91 =3D=3D "JTST" || CYGHWR_HAL_AR= M_AT91 =3D=3D "JPMC" ? 115200 : 38400} description " This option selects the baud rate used for the diagnostic port= ." } @@ -173,7 +173,7 @@ display "GDB serial port baud rate" flavor data legal_values 9600 19200 38400 57600 115200 - default_value 38400 + default_value {CYGHWR_HAL_ARM_AT91 =3D=3D "JTST" || CYGHWR_HAL_A= RM_AT91 =3D=3D "JPMC" ? 115200 : 38400} description " This option controls the baud rate used for the GDB connection= ." } Index: var/current/include/var_arch.h =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/include/var_arch= .h,v retrieving revision 1.1 diff -u -r1.1 var_arch.h --- var/current/include/var_arch.h 24 Jun 2003 08:42:26 -0000 1.1 +++ var/current/include/var_arch.h 7 Jun 2004 13:45:09 -0000 @@ -81,8 +81,10 @@ HAL_WRITE_UINT32(AT91_PMC+AT91_PMC_SCDR, 1); \ CYG_MACRO_END =20 -#else +#elif defined(CYGHWR_HAL_ARM_AT91_JTST) || \ + defined(CYGHWR_HAL_ARM_AT91_DJPMC) =20 +#else #error Unknown AT91 variant =20 #endif Index: var/current/include/var_io.h =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/include/var_io.h= ,v retrieving revision 1.7 diff -u -r1.7 var_io.h --- var/current/include/var_io.h 24 May 2004 08:41:47 -0000 1.7 +++ var/current/include/var_io.h 7 Jun 2004 13:45:10 -0000 @@ -44,7 +44,7 @@ //#####DESCRIPTIONBEGIN#### // // Author(s): jskov -// Contributors:jskov, gthomas, tkoeller, tdrury, nickg +// Contributors:jskov, gthomas, tkoeller, tdrury, nickg, amichelotti // Date: 2001-07-12 // Purpose: AT91 variant specific registers // Description:=20 @@ -57,6 +57,122 @@ #include =20 //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D +#if defined(CYGHWR_HAL_ARM_AT91_JTST) || \ + defined(CYGHWR_HAL_ARM_AT91_DJPMC) + +// mapping diopsis internal resources +#define AT91_USART0 0xFFFC0000 +#define AT91_USART1 0xFFFC4000 +#define AT91_SPI0 0xFFFC8000 +#define AT91_SPI1 0xFFFCC000 + +#define AT91_PIO 0xFFFF0000 +#define AT91_AIC 0xFFFFF000 +#define AT91_TC 0xFFFEC000 +#define AT91_EBI 0xFFFE4000 +#define AT91_WD 0xFFFF8000 +#define AT91_CLKGEN 0xFFF00000 // clock divider +#define AT91_ADDA 0xFFF08000 // ADDA Analog Digital Digital Analog + + +// SPI interface +#define AT91_SPI_CR 0x0 // control register +#define AT91_SPI_MR 0x4 // mode register +#define AT91_SPI_RDR 0x8 // receive data register +#define AT91_SPI_TDR 0x8 // trasmit data register +#define AT91_SPI_SR 0x10 // status register +#define AT91_SPI_IER 0x14 // interrupt register +#define AT91_SPI_IDR 0x18 // interrupt disable register +#define AT91_SPI_IMR 0x10 // interrupt mask register +#define AT91_SPI_CSR0 0x30 // chip select 0 +#define AT91_SPI_CSR1 0x34 // chip select 1 +#define AT91_SPI_CSR2 0x38 // chip select 2 +#define AT91_SPI_CSR3 0x3C // chip select 3 + + +// CLOCK divider interface + +#define AT91_CLKGEN_CPTMAX0 0x0 //counter 0 +#define AT91_CLKGEN_CPTMAX1 0x4 //counter 1 +#define AT91_CLKGEN_CPTMAX2 0x8 //.. +#define AT91_CLKGEN_CPTMAX3 0xC +#define AT91_CLKGEN_CPTMAX4 0x10 +#define AT91_CLKGEN_CPTMAX5 0x14 +#define AT91_CLKGEN_CPTMAX6 0x18 +#define AT91_CLKGEN_CPTMAX7 0x1C +#define AT91_CLKGEN_CPTMAX8 0x20 +#define AT91_CLKGEN_CLKENABLE 0x24 // enable clocks out, wronly +#define AT91_CLKGEN_CLKDISABLE 0x28 // disable clocks out, wronly + +// ADDA Analog Digital Digital Analog interface + +#define AT91_ADDA_CR 0x0 // adda configuration +#define AT91_ADDA_ADCL0 0x20 // ADC input channel0 LEFT +#define AT91_ADDA_ADCR0 0x24 // ADC input channel0 RIGHT +#define AT91_ADDA_ADCL1 0x28 // ADC input channel1 LEFT +#define AT91_ADDA_ADCR1 0x2C // ADC input channel1 RIGHT +#define AT91_ADDA_ADCL2 0x30 // ADC input channel2 LEFT +#define AT91_ADDA_ADCR2 0x34 // ADC input channel2 RIGHT +#define AT91_ADDA_ADCL3 0x38 // ADC input channel3 LEFT +#define AT91_ADDA_ADCR3 0x3C // ADC input channel3 RIGHT + +#define AT91_ADDA_DACL0 0x20 // DAC output channel0 LEFT +#define AT91_ADDA_DACR0 0x24 // DAC output channel0 RIGHT +#define AT91_ADDA_DACL1 0x28 // DAC output channel1 LEFT +#define AT91_ADDA_DACR1 0x2C // DAC output channel1 RIGHT +#define AT91_ADDA_DACL2 0x30 // DAC output channel2 LEFT +#define AT91_ADDA_DACR2 0x34 // DAC output channel2 RIGHT +#define AT91_ADDA_DACL3 0x38 // DAC output channel3 LEFT +#define AT91_ADDA_DACR4 0x3C // DAC output channel3 RIGHT + + +///// MAGIC DSP +// Magic Data Memory Left BASE 40 bit width (64 bit aligned) +#define AT91_MAARDML 0x00410000 +// Magic Data Memory Right BASE 40 bit width (64 bit aligned) +#define AT91_MAARDMR 0x00420000 +// Magic Parm Left Base (arm interchange memory) 40 bit width (64 bit ali= gned) +#define AT91_MAARPARML 0x00490000 +// Magic Parm Right Base (arm interchange memory) 40 bit width (64 bit al= igned) +#define AT91_MAARPARMR 0x004A0000 +// Magic Program Memory +#define AT91_MAARPM 0x00430000 + +// Magic Global Controller registers=20 +#define AT91_MAARGSR 0x00450000 +#define AT91_MAARGSR_SAR 0x0 // start magic program address +#define AT91_MAARGSR_CONF 0x4 // magic configuration +#define AT91_MAARGSR_STAT 0x8 // magic status rdonly +#define AT91_MAARGSR_EXC 0xC // magic exception rdonly +#define AT91_MAARGSR_EXC_MSK 0x10 // magic exception mask=20 +#define AT91_MAARGSR_PC 0x14 // magic program counter +#define AT91_MAARGSR_QCS 0x18 // magic condition stack Q +#define AT91_MAARGSR_ICS 0x1C // magic condition stack I +#define AT91_MAARGSR_PMS 0x20 // magic pma stack +#define AT91_MAARGSR_DMA_TYPE 0x24 // magic dma type +#define AT91_MAARGSR_DMA_LEN 0x28 // magic dma len +#define AT91_MAARGSR_DMA_MOD 0x2C // magic modifier/stride +#define AT91_MAARGSR_DMA_BADD 0x30 // magic dma buffer address (inter= nal address) +#define AT91_MAARGSR_DMA_XADD 0x34 // magic dma external address +#define AT91_MAARGSR_DMA_START 0x38 // magic start dma +#define AT91_MAARGSR_STEP_MODE 0x3C // magic single cycle mode + + + +// Magic MAAR (MAgic ARm interface) Controller registers base +#define AT91_MAARCSE 0x00460000 +#define AT91_MAARCSE_CMD 0x0 // command register +#define AT91_MAARCSE_CMD_RUN 0x1 // run +#define AT91_MAARCSE_SR 0x4 // status register +#define AT91_MAARCSE_EXC 0x8 // exception register +#define AT91_MAARCSE_EXC_MSK 0xC // mask exception register + + +// usarts are connected to clock divider +#define AT91_US_BAUD(baud) (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/(16*(baud))) + +#endif + // USART =20 #ifndef AT91_USART0 @@ -135,8 +251,9 @@ #define AT91_US_TPR 0x38 // Transmit pointer register #define AT91_US_TCR 0x3c // Transmit counter register =20 +#ifndef AT91_US_BAUD #define AT91_US_BAUD(baud) ((CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/(8*(baud))+1)= /2) - +#endif //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D // PIO =20 @@ -610,8 +727,9 @@ =20 #endif =20 +#elif defined(CYGHWR_HAL_ARM_AT91_JTST) || \ + defined(CYGHWR_HAL_ARM_AT91_DJPMC) #else - #error Unknown AT91 variant =20 #endif Index: var/current/src/at91_misc.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/src/at91_misc.c,v retrieving revision 1.7 diff -u -r1.7 at91_misc.c --- var/current/src/at91_misc.c 28 Oct 2003 18:09:07 -0000 1.7 +++ var/current/src/at91_misc.c 7 Jun 2004 13:45:10 -0000 @@ -82,10 +82,15 @@ =20 // Disable counter HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_CLKDIS); - +#if defined(CYGHWR_HAL_ARM_AT91_JTST) || \ + defined(CYGHWR_HAL_ARM_AT91_DJPMC) + HAL_WRITE_UINT32(timer+AT91_TC_CMR, AT91_TC_CMR_CPCTRG | // Res= et counter on CPC + AT91_TC_CMR_CLKS_MCK8); // 1 MH= z from CLOCKGEN +#else // Set registers HAL_WRITE_UINT32(timer+AT91_TC_CMR, AT91_TC_CMR_CPCTRG | // Res= et counter on CPC AT91_TC_CMR_CLKS_MCK32); // 1 M= Hz +#endif HAL_WRITE_UINT32(timer+AT91_TC_RC, period); =20 // Start timer @@ -127,7 +132,12 @@ // void hal_delay_us(cyg_int32 usecs) { - CYG_ADDRESS timer =3D AT91_TC+AT91_TC_TC2; +#if defined(CYGHWR_HAL_ARM_AT91_JTST) || \ + defined(CYGHWR_HAL_ARM_AT91_DJPMC) + CYG_ADDRESS timer =3D AT91_TC+AT91_TC_TC1; // Use timer counter 1, timer= counter2 it's used with AD/DA converter +#else + CYG_ADDRESS timer =3D AT91_TC+AT91_TC_TC2; +#endif cyg_uint32 stat; cyg_uint64 ticks; =20 @@ -140,7 +150,12 @@ HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_CLKDIS); =20 // Set registers +#if defined(CYGHWR_HAL_ARM_AT91_JTST) || \ + defined(CYGHWR_HAL_ARM_AT91_DJPMC) + HAL_WRITE_UINT32(timer+AT91_TC_CMR, AT91_TC_CMR_CLKS_MCK8); // MCK8 = =3D1 points to clockgen =3D> 1MHz +#else HAL_WRITE_UINT32(timer+AT91_TC_CMR, AT91_TC_CMR_CLKS_MCK32); // 1MHz +#endif HAL_WRITE_UINT32(timer+AT91_TC_RA, 0); HAL_WRITE_UINT32(timer+AT91_TC_RC, ticks); =20 @@ -188,7 +203,7 @@ // No valid interrrupt source, treat as spurious interrupt=20=20=20=20 if (irq_num < CYGNUM_HAL_ISR_MIN || irq_num > CYGNUM_HAL_ISR_MAX) irq_num =3D CYGNUM_HAL_INTERRUPT_NONE; -=20=20=20=20 + return irq_num; } =20 ------=_NextPart_000_010F_01C44CAC.1B893800--