Index: src/cpm.c =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/quicc/current/src/cpm.c,v retrieving revision 1.3.2.1 diff -u -5 -p -r1.3.2.1 cpm.c --- src/cpm.c 20 Mar 2003 18:49:10 -0000 1.3.2.1 +++ src/cpm.c 31 Mar 2003 15:33:01 -0000 @@ -55,10 +55,11 @@ #include #include #include #include +#include // memset #ifdef CYGPKG_HAL_POWERPC_MPC860 // eCos headers decribing PowerQUICC: #include @@ -73,19 +74,19 @@ static short *nextBd = (short *)(CYGHWR_ void _mpc8xx_reset_cpm(void) { EPPC *eppc = eppc_base(); - int i; static int init_done = 0; if (init_done) return; init_done++; eppc->cp_cr = QUICC_CPM_CR_RESET | QUICC_CPM_CR_BUSY; - memset(eppc->pram, 0, 0x400); - for (i = 0; i < 100000; i++); + memset(eppc->pram, 0, sizeof(eppc->pram)); + while (eppc->cp_cr & QUICC_CPM_CR_BUSY) + CYG_EMPTY_STATEMENT; *nextBd = QUICC_BD_BASE; } // Index: src/quicc_smc1.c =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/quicc/current/src/quicc_smc1.c,v retrieving revision 1.23.2.1 diff -u -5 -p -r1.23.2.1 quicc_smc1.c --- src/quicc_smc1.c 20 Mar 2003 18:49:10 -0000 1.23.2.1 +++ src/quicc_smc1.c 31 Mar 2003 15:33:01 -0000 @@ -71,10 +71,11 @@ #include // target_register_t #include // HAL_INTERRUPT_UNMASK(...) #include // Calling interface definitions #include // Helper functions #include // CYG_ISR_HANDLED +#include // memset #define UART_BIT_RATE(n) (((int)(CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000)/16)/n) #define UART_BAUD_RATE CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD // Note: buffers will be placed just after descriptors @@ -149,12 +150,10 @@ cyg_hal_smcx_init_channel(struct port_in struct cp_bufdesc *txbd, *rxbd; if (info->init) return; info->init = 1; - _mpc8xx_reset_cpm(); - switch (port) { #if CYGNUM_HAL_QUICC_SMC1 > 0 case QUICC_CPM_SMC1: /* * Set up the PortB pins for UART operation. @@ -253,11 +252,11 @@ cyg_hal_smcx_init_channel(struct port_in /* * Clear any previous events. Mask interrupts. * (Section 16.15.7.14 and 16.15.7.15) */ regs->smc_smce = 0xff; - regs->smc_smcm = 5; + regs->smc_smcm = 1; // RX interrupts only, for ctrl-c /* * Set 8,n,1 characters, then also enable rx and tx. * (Section 16.15.7.11) */ @@ -585,12 +584,10 @@ cyg_hal_sccx_init_channel(struct port_in struct cp_bufdesc *txbd, *rxbd; if (info->init) return; info->init = 1; - _mpc8xx_reset_cpm(); - /* * Set up the Port pins for UART operation. */ switch (port) { #if CYGNUM_HAL_QUICC_SCC1 > 0 @@ -732,12 +729,11 @@ cyg_hal_sccx_init_channel(struct port_in /* * Clear any previous events. Mask interrupts. * (Section 16.15.7.14 and 16.15.7.15) */ regs->scc_scce = 0xffff; - regs->scc_sccm = 5; - regs->scc_sccm = 3; + regs->scc_sccm = 1; // RX interrupts only, for ctrl-c /* * Set 8,n,1 characters */ regs->scc_psmr = (3<<12);