Index: ChangeLog =================================================================== RCS file: /cvs/ecos/ecos/packages/devs/eth/arm/ks32c5000/current/ChangeLog,v retrieving revision 1.8 retrieving revision 1.12 diff -u -5 -p -r1.8 -r1.12 --- ChangeLog 5 Nov 2002 02:49:50 -0000 1.8 +++ ChangeLog 27 Mar 2003 17:26:37 -0000 1.12 @@ -1,5 +1,39 @@ +2003-03-27 Jay Foster + + * src/ics1890.c: Added configurable PHY MII address. + * src/lxt970.c: Added configurable PHY MII address. + * src/lxt972.c: Added configurable PHY MII address. + * cdl/ks32c5000_eth.cdl: CDL to allow configuration of the PHY + MII address. Documented support for ICS1893AF PHY. + * src/ks5000_ether.c: Added configurable PHY MII address. + Fixed local definition of eth_drv_init() macro (produces no code + change). Fixed strncpy()s for the ETH_DRV_GET_IF_STATS IOCTL to + leave room for the NUL termination character and use parenthesis + with the 'sizeof' operator. Added ETH_DRV_SET_MAC_ADDRESS IOCTL + support to allow setting the MAC (ESA) address from the application. + Fixed to only attach the CYGNUM_HAL_INTERRUPT_EXT0 if the + HavePHYinterrupt conditional is defined. This prevents unhandled + interrupts from getting through when HavePHYinterrupt is not defined. + +2003-03-26 Chris Garry + + * cdl/ks32c5000_eth.cdl + * src/ks5000_ether.c: Added CDL control for level of driver + debug output. + +2003-03-20 Chris Garry + + * src/ks5000_ether.c: + Added volatile to *rxReadPointer, *txDonePointer and + *txWritePointer's definitions. + +2003-02-20 Chris Garry + + * src/ks5000_ether.c: + Removed line setting up programmable I/O pins as debug outputs. + 2002-11-05 Jonathan Larmour * cdl/ks32c5000_eth.cdl: Ensure exactly 1 PHY enabled. 2002-11-05 Chris Garry Index: cdl/ks32c5000_eth.cdl =================================================================== RCS file: /cvs/ecos/ecos/packages/devs/eth/arm/ks32c5000/current/cdl/ks32c5000_eth.cdl,v retrieving revision 1.5 retrieving revision 1.7 diff -u -5 -p -r1.5 -r1.7 --- cdl/ks32c5000_eth.cdl 5 Nov 2002 02:50:13 -0000 1.5 +++ cdl/ks32c5000_eth.cdl 27 Mar 2003 17:26:37 -0000 1.7 @@ -75,19 +75,34 @@ cdl_package CYGPKG_DEVS_ETH_ARM_KS32C500 cdl_interface CYGINT_DEVS_ETH_ARM_KS32C5000_PHY { display "PHY support" } + cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_DEBUG_LEVEL { + display "KS32C5000 device driver debug output level" + flavor data + legal_values {0 1 2} + default_value 1 + description " + This option specifies the level of debug data output by the + KS32C5000 device driver. A value of 0 signifies no debug data + output; 1 signifies normal debug data output; and 2 signifies + maximum debug data output (not suitable when GDB and + application are sharing an ethernet port)." + } + cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_ICS1890 { display "ICS1890 PHY support" flavor bool default_value 0 implements CYGINT_DEVS_ETH_ARM_KS32C5000_PHY compile -library=libextras.a ics1890.c + description "This component provides support for the ICS1890 and + ICS1893AF PHY" } - cdl_component CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT970 { + cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT970 { display "LXT970 PHY support" flavor bool default_value 1 implements CYGINT_DEVS_ETH_ARM_KS32C5000_PHY compile -library=libextras.a lxt970.c @@ -99,39 +114,47 @@ cdl_package CYGPKG_DEVS_ETH_ARM_KS32C500 default_value 0 implements CYGINT_DEVS_ETH_ARM_KS32C5000_PHY compile -library=libextras.a lxt972.c no_define - cdl_component CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT972_LED1 { + cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT972_LED1 { display "LED 1 mode" flavor data legal_values {"LINK_SPEED" "TX_ACTIVITY" "RX_ACTIVITY" "COLLISION_STATUS" "LINK_STATUS" "DUPLEX_STATUS" "LINK_ACTIVITY" "LINK_STATUS_RX_STATUS_COMBINED" "LINK_STATUS_LINK_ACTIVITY_COMBINED" "DUPLEX_STATUS_COLLISION_STATUS_COMBINED" "TEST_ON" "TEST_OFF" "TEST_BLINK_FAST" "TEST_BLINK_SLOW"} default_value {"LINK_STATUS"} } - cdl_component CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT972_LED2 { + cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT972_LED2 { display "LED 2 mode" flavor data legal_values {"LINK_SPEED" "TX_ACTIVITY" "RX_ACTIVITY" "COLLISION_STATUS" "LINK_STATUS" "DUPLEX_STATUS" "LINK_ACTIVITY" "LINK_STATUS_RX_STATUS_COMBINED" "LINK_STATUS_LINK_ACTIVITY_COMBINED" "DUPLEX_STATUS_COLLISION_STATUS_COMBINED" "TEST_ON" "TEST_OFF" "TEST_BLINK_FAST" "TEST_BLINK_SLOW"} default_value {"LINK_SPEED"} } - cdl_component CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT972_LED3 { + cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT972_LED3 { display "LED 3 mode" flavor data legal_values {"LINK_SPEED" "TX_ACTIVITY" "RX_ACTIVITY" "COLLISION_STATUS" "LINK_STATUS" "DUPLEX_STATUS" "LINK_ACTIVITY" "LINK_STATUS_RX_STATUS_COMBINED" "LINK_STATUS_LINK_ACTIVITY_COMBINED" "DUPLEX_STATUS_COLLISION_STATUS_COMBINED" "TEST_ON" "TEST_OFF" "TEST_BLINK_FAST" "TEST_BLINK_SLOW"} default_value {"LINK_ACTIVITY"} } + } + + cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR { + display "PHY MII address" + flavor data + legal_values 0 to 31 + default_value 1 + description "This option specifies the MII address of the PHY" } cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_MACADDR { display "Ethernet address for eth0" flavor data Index: src/ics1890.c =================================================================== RCS file: /cvs/ecos/ecos/packages/devs/eth/arm/ks32c5000/current/src/ics1890.c,v retrieving revision 1.2 retrieving revision 1.3 diff -u -5 -p -r1.2 -r1.3 --- src/ics1890.c 23 May 2002 23:00:40 -0000 1.2 +++ src/ics1890.c 27 Mar 2003 17:26:38 -0000 1.3 @@ -65,11 +65,15 @@ #define PHY_ECNTL_REG1 0x10 #define PHY_QPDS_REG 0x11 #define PHY_10BOP_REG 0x12 #define PHY_ECNTL_REG2 0x13 -#define PHYHWADDR 0x20 +#ifdef CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR +#define PHYHWADDR CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR +#else +#define PHYHWADDR 1 +#endif #define Bit(n) (1<<(n)) #define RESET_PHY Bit(15) #define ENABLE_LOOPBACK Bit(14) Index: src/ks5000_ether.c =================================================================== RCS file: /cvs/ecos/ecos/packages/devs/eth/arm/ks32c5000/current/src/ks5000_ether.c,v retrieving revision 1.7 retrieving revision 1.11 diff -u -5 -p -r1.7 -r1.11 --- src/ks5000_ether.c 5 Nov 2002 02:24:43 -0000 1.7 +++ src/ks5000_ether.c 27 Mar 2003 17:26:38 -0000 1.11 @@ -58,11 +58,11 @@ #if defined(CYGPKG_IO) #include #include #include #else -// need to prvide fake values for errno +// need to provide fake values for errno #define EIO 1 #define EINVAL 2 #endif #include // Common type definitions and support @@ -98,15 +98,22 @@ #if HavePHY #include "phy.h" #endif -#if 1 -#define debug_printf(args...) diag_printf(args) +// Set up the level of debug output +#if CYGPKG_DEVS_ETH_ARM_KS32C5000_DEBUG_LEVEL > 0 +#define debug1_printf(args...) diag_printf(args) #else -#define debug_printf(args...) /* noop */ +#define debug1_printf(args...) /* noop */ #endif +#if CYGPKG_DEVS_ETH_ARM_KS32C5000_DEBUG_LEVEL > 1 +#define debug2_printf(args...) diag_printf(args) +#else +#define debug2_printf(args...) /* noop */ +#endif + #define Bit(n) (1<<(n)) // enable/disable software verification of rx CRC // should be moved to user-controlled valud in CDL file @@ -125,24 +132,24 @@ #define MiiStart 0x0800 void MiiStationWrite(U32 RegAddr, U32 PhyAddr, U32 PhyWrData) { STADATA = PhyWrData ; - STACON = RegAddr | PhyAddr | MiiStart | PHYREGWRITE ; + STACON = RegAddr | (PhyAddr<<5) | MiiStart | PHYREGWRITE ; while (STACON & MiiStart) ; - //debug_printf("PHY Wr %x:%02x := %04x\n",PhyAddr, RegAddr, PhyWrData) ; + //debug1_printf("PHY Wr %x:%02x := %04x\n",PhyAddr, RegAddr, PhyWrData) ; } U32 MiiStationRead(U32 RegAddr, U32 PhyAddr) { U32 PhyRdData; - STACON = RegAddr | PhyAddr | MiiStart; + STACON = RegAddr | (PhyAddr<<5) | MiiStart; while (STACON & MiiStart) ; PhyRdData = STADATA; - //debug_printf("PHY Rd %x:%02x %04x\n",PhyAddr,RegAddr,PhyRdData) ; + //debug1_printf("PHY Rd %x:%02x %04x\n",PhyAddr,RegAddr,PhyRdData) ; return PhyRdData ; } #endif // miscellaneous data structures @@ -305,13 +312,13 @@ static FRAME_DESCRIPTOR _txFrameDescrArr /* define aliases that will set the no-cache bit */ #define rxFrameDescrArray ((FRAME_DESCRIPTOR*)(((unsigned)_rxFrameDescrArray)|0x4000000)) #define txFrameDescrArray ((FRAME_DESCRIPTOR*)(((unsigned)_txFrameDescrArray)|0x4000000)) -static FRAME_DESCRIPTOR *rxReadPointer; -static FRAME_DESCRIPTOR *txDonePointer; -static FRAME_DESCRIPTOR *txWritePointer; +static volatile FRAME_DESCRIPTOR *rxReadPointer; +static volatile FRAME_DESCRIPTOR *txDonePointer; +static volatile FRAME_DESCRIPTOR *txWritePointer; static cyg_drv_mutex_t oldRxMutex; static cyg_drv_cond_t oldRxCond; @@ -474,12 +481,10 @@ static int ks32c5000_eth_buffer_send(tEt #if defined(CYGPKG_NET) while (!configDone) cyg_thread_delay(10); #endif - //diag_printf("Phy Status = %x\n",PhyStatus()); - if (txWritePointer->FrameDataPtr & FRM_OWNERSHIP_BDMA) { // queue is full! make sure transmit is running BDMATXCON |= BDMATXCON_EN; MACTXCON |= MACTXCON_TX_EN; @@ -629,15 +634,15 @@ static tEthBuffer *ks32c5000_eth_get_rec //====================================================================== static int EthInit(U08* mac_address) { if (mac_address) - debug_printf("EthInit(%02x:%02x:%02x:%02x:%02x:%02x)\n", + debug2_printf("EthInit(%02x:%02x:%02x:%02x:%02x:%02x)\n", mac_address[0],mac_address[1],mac_address[2], mac_address[3],mac_address[4],mac_address[5]); else - debug_printf("EthInit(NULL)\n"); + debug2_printf("EthInit(NULL)\n"); #if HavePHY PhyReset(); #endif @@ -677,22 +682,22 @@ static int EthInit(U08* mac_address) MACRXCON = MACRxConfigVar; BDMATXCON = BDMATxConfigVar; MACTXCON = MACTxConfigVar; - diag_printf("ks32C5000 eth: %02x:%02x:%02x:%02x:%02x:%02x ", + debug2_printf("ks32C5000 eth: %02x:%02x:%02x:%02x:%02x:%02x ", *((volatile unsigned char*)CAM_BaseAddr+0), *((volatile unsigned char*)CAM_BaseAddr+1), *((volatile unsigned char*)CAM_BaseAddr+2), *((volatile unsigned char*)CAM_BaseAddr+3), *((volatile unsigned char*)CAM_BaseAddr+4), *((volatile unsigned char*)CAM_BaseAddr+5)); #if SoftwareCRC - diag_printf("Software CRC\n"); + debug2_printf("Software CRC\n"); #else - diag_printf("Hardware CRC\n"); + debug2_printf("Hardware CRC\n"); #endif return 0; } @@ -765,13 +770,13 @@ static cyg_uint32 MAC_Phy_isr(cyg_vector cyg_drv_interrupt_acknowledge(vector); PhyInterruptAck(); ++ks5000_MAC_Phy_Cnt; linkStatus = PhyStatus(); if (linkStatus & PhyStatus_FullDuplex) - MACConfigVar |= (1<<3); + MACConfigVar |= (MACON_FULL_DUP); else - MACConfigVar &= ~(1<<3); + MACConfigVar &= ~(MACON_FULL_DUP); #if defined(CYGPKG_NET) if (linkStatus & PhyStatus_FullDuplex) ifStats.duplex = 3; else @@ -938,12 +943,12 @@ static cyg_uint32 BDMA_Tx_isr(cyg_vector #if defined(CYGPKG_NET) ++ifStats.interrupts; #endif if (IntBDMATxStatus & BDMASTAT_TX_CCP) { - debug_printf("+-- Control Packet Transfered : %x\r",ERMPZCNT); - debug_printf(" Tx Control Frame Status : %x\r",ETXSTAT); + debug1_printf("+-- Control Packet Transfered : %x\r",ERMPZCNT); + debug1_printf(" Tx Control Frame Status : %x\r",ETXSTAT); } if (IntBDMATxStatus & (BDMASTAT_TX_NL|BDMASTAT_TX_NO|BDMASTAT_TX_EMPTY) ) { if (IntBDMATxStatus & BDMASTAT_TX_NL) @@ -1064,11 +1069,11 @@ static void ks32c5000_eth_deliver(struct static void installInterrupts(void) { extern struct eth_drv_sc ks32c5000_sc; bool firstTime=true; - debug_printf("ks5000_ether: installInterrupts()\n"); + debug1_printf("ks5000_ether: installInterrupts()\n"); if (!firstTime) return; firstTime = false; @@ -1095,12 +1100,14 @@ static void installInterrupts(void) cyg_drv_interrupt_attach(bdmaRxIntrHandle); cyg_drv_interrupt_attach(bdmaTxIntrHandle); cyg_drv_interrupt_attach(macRxIntrHandle); cyg_drv_interrupt_attach(macTxIntrHandle); +#if HavePHYinterrupt cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_EXT0); cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_EXT0); +#endif } //====================================================================== // Driver code that interfaces to the TCP/IP stack via the common // Ethernet interface. @@ -1113,22 +1120,20 @@ typedef struct }ks32c5000_priv_data_t; ks32c5000_priv_data_t ks32c5000_priv_data; #define eth_drv_tx_done(sc,key,retval) (sc)->funs->eth_drv->tx_done(sc,key,retval) -#define eth_drv_init(sc,enaddr) ((sc)->funs->eth_drv->init)(sc, myMacAddr) +#define eth_drv_init(sc,enaddr) ((sc)->funs->eth_drv->init)(sc, enaddr) #define eth_drv_recv(sc,len) ((sc)->funs->eth_drv->recv)(sc, len) static unsigned char myMacAddr[6] = { CYGPKG_DEVS_ETH_ARM_KS32C5000_MACADDR }; static bool ks32c5000_eth_init(struct cyg_netdevtab_entry *tab) { struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance; - *(unsigned*)0x7ff5000 |= Bit(1)+Bit(3)+Bit(5); // enable debug output bits - // memcpy(myMacAddr,(unsigned char*)CAM_BaseAddr,6); - debug_printf("ks32c5000_eth_init()\n"); - debug_printf(" MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",myMacAddr[0],myMacAddr[1],myMacAddr[2],myMacAddr[3],myMacAddr[4],myMacAddr[5]); + debug1_printf("ks32c5000_eth_init()\n"); + debug1_printf(" MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",myMacAddr[0],myMacAddr[1],myMacAddr[2],myMacAddr[3],myMacAddr[4],myMacAddr[5]); #if defined(CYGPKG_NET) ifStats.duplex = 1; //unknown ifStats.operational = 1; //unknown ifStats.tx_queue_len = MAX_TX_FRAME_DESCRIPTORS; #endif @@ -1144,11 +1149,11 @@ static bool ks32c5000_eth_init(struct cy return true; } static void ks32c5000_eth_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags) { - debug_printf("ks32c5000_eth_start()\n"); + debug2_printf("ks32c5000_eth_start()\n"); if (!ethernetRunning) { cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_ETH_BDMA_RX); cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_ETH_BDMA_TX); cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_ETH_MAC_RX); @@ -1162,11 +1167,11 @@ static void ks32c5000_eth_start(struct e } } static void ks32c5000_eth_stop(struct eth_drv_sc *sc) { - debug_printf("ks32c5000_eth_stop()\n"); + debug1_printf("ks32c5000_eth_stop()\n"); ethernetRunning = 0; } static int ks32c5000_eth_control(struct eth_drv_sc *sc, unsigned long cmd, @@ -1179,15 +1184,38 @@ static int ks32c5000_eth_control(struct case ETH_DRV_GET_IF_STATS_UD: case ETH_DRV_GET_IF_STATS: { struct ether_drv_stats *p = (struct ether_drv_stats*)data; *p = ifStats; - strncpy(p->description,"description goes here",sizeof p->description); - strncpy(p->snmp_chipset,"chipset name",sizeof p->snmp_chipset); + strncpy(p->description,"description goes here",sizeof(p->description)-1); + p->description[sizeof(p->description)-1] = '\0'; + strncpy(p->snmp_chipset,"chipset name",sizeof(p->snmp_chipset)-1); + p->snmp_chipset[sizeof(p->snmp_chipset)-1] = '\0'; return 0; } #endif + case ETH_DRV_SET_MAC_ADDRESS: { + int act; + + if (ETHER_ADDR_LEN != len) + return -1; + debug1_printf("ks32c5000_eth_control: ETH_DRV_SET_MAC_ADDRESS.\n"); + act = ethernetRunning; + ks32c5000_eth_stop(sc); + ks32c5000_eth_start(sc, data, 0); + ethernetRunning = act; + return 0; + } +#ifdef ETH_DRV_GET_MAC_ADDRESS + case ETH_DRV_GET_MAC_ADDRESS: { + if (len < ETHER_ADDR_LEN) + return -1; + debug1_printf("ks32c5000_eth_control: ETH_DRV_GET_MAC_ADDRESS.\n"); + memcpy(data, (void *)CAM_BaseAddr, ETHER_ADDR_LEN); + return 0; + } +#endif default: return -1; } } Index: src/lxt970.c =================================================================== RCS file: /cvs/ecos/ecos/packages/devs/eth/arm/ks32c5000/current/src/lxt970.c,v retrieving revision 1.3 retrieving revision 1.4 diff -u -5 -p -r1.3 -r1.4 --- src/lxt970.c 5 Nov 2002 02:49:51 -0000 1.3 +++ src/lxt970.c 27 Mar 2003 17:26:38 -0000 1.4 @@ -53,11 +53,15 @@ #include "std.h" #include "phy.h" // address of the LX970 phy -#define LX970_ADDR 0x20 +#ifdef CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR +#define LX970_ADDR CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR +#else +#define LX970_ADDR 1 +#endif // LX970 register offsets #define LX970_CNTL_REG 0x00 #define LX970_STATUS_REG 0x01 #define LX970_ID_REG1 0x02 Index: src/lxt972.c =================================================================== RCS file: /cvs/ecos/ecos/packages/devs/eth/arm/ks32c5000/current/src/lxt972.c,v retrieving revision 1.1 retrieving revision 1.2 diff -u -5 -p -r1.1 -r1.2 --- src/lxt972.c 5 Nov 2002 02:50:43 -0000 1.1 +++ src/lxt972.c 27 Mar 2003 17:26:38 -0000 1.2 @@ -57,11 +57,15 @@ #include "phy.h" #define Bit(n) (1<<(n)) // address of the LX972 phy -#define LX972_ADDR 0x00 +#ifdef CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR +#define LX972_ADDR CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR +#else +#define LX972_ADDR 0 +#endif // LX972 register offsets #define LX972_CTRL_REG 0x00 #define LX972_STATUS1_REG 0x01 #define LX972_PHY_ID1_REG 0x02