Support for atsam7x512

Support for atsam7x512

[John Eigelaar]

[-- Attachment #1: Type: text/plain, Size: 465 bytes --]

Hi,

Here is a patch that adds all the CDL options and the necessary memory
layout files to support 
the Atmel at91sam7x512 as part of the at91sam7s HAL.

I also fixed a small typo in the at91sam7xek phy setup code whereby the
powerdown pin (GPIO PB18)is 
configured as an an output but then GPIO PB19 is driven low instead of
the intended poerdown line.

Regards
John Eigelaar

PS Any body know a way of incorporating the newly created files into the
patch file ?

[-- Attachment #2: at91sam7x512.patch --]
[-- Type: application/octet-stream, Size: 5179 bytes --]

? packages/hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7x512_rom.h
? packages/hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7x512_rom.ldi
Index: packages/hal/arm/at91/at91sam7s/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/ChangeLog,v
retrieving revision 1.13
diff -u -r1.13 ChangeLog
--- packages/hal/arm/at91/at91sam7s/current/ChangeLog	23 Apr 2008 08:17:44 -0000	1.13
+++ packages/hal/arm/at91/at91sam7s/current/ChangeLog	30 Apr 2008 14:01:35 -0000
@@ -1,3 +1,10 @@
+2008-04-30  John Eigelaar  <jeigelaar@mweb.co.za>
+
+	* include/pkgconf/mlt_arm_at91sam7x512_rom.{h|ldi}: Added the 
+	memory layout files to support the at91sam7x512  
+	* cdl/hal_arm_at91s.cdl: Added the configuration options to 
+	support the at91sam7x512
+	
 2008-04-23  Andrew Lunn  <andrew.lunn@ascom.ch>
 
 	* include/hal_platform_setup.h: Fix setting the flash wait states
Index: packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl,v
retrieving revision 1.7
diff -u -r1.7 hal_arm_at91sam7s.cdl
--- packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl	26 Mar 2007 10:42:44 -0000	1.7
+++ packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl	30 Apr 2008 13:08:33 -0000
@@ -78,7 +78,7 @@
         default_value  {"at91sam7s256"}
         legal_values   {"at91sam7s32" "at91sam7s321" "at91sam7s64" 
                         "at91sam7s128" "at91sam7s256" 
-                        "at91sam7x128" "at91sam7x256" 
+                        "at91sam7x128" "at91sam7x256" "at91sam7x512" 
                         "at91sam7xc128" "at91sam7xc256" }
         description    "
            The AT91SAM7 microcontroller family has several variants,
@@ -101,7 +101,8 @@
 
     cdl_option CYGHWR_HAL_ARM_AT91SAM7X {
         display     "SAM7X device" 
-        calculated  { CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7x256" ||
+        calculated  { CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7x512" ||
+	              CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7x256" ||
                       CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7x128" }        
         description "
             Is the AT91SAM7 device a member of the AT91SAM7X family?"
Index: packages/hal/arm/at91/at91sam7xek/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7xek/current/ChangeLog,v
retrieving revision 1.3
diff -u -r1.3 ChangeLog
--- packages/hal/arm/at91/at91sam7xek/current/ChangeLog	5 Mar 2007 19:09:32 -0000	1.3
+++ packages/hal/arm/at91/at91sam7xek/current/ChangeLog	30 Apr 2008 14:08:40 -0000
@@ -1,3 +1,11 @@
+2008-04-30  John Eigelaar <jeigelaar@mweb.co.za>
+
+        * cdl/hal_arm_at91sam7xek.cdl: Added configuration options in 
+	order to support the at91sam7x512
+	* src/at91sam7xek_misc.c: Fix a typo in the phy initialisation code.
+	Pin 18 was being setup to drive the powerdown pin of the phy but 
+	pin 19 was driven low instead.
+
 2007-01-17  John Eigelaar <jeigelaar@mweb.co.za>
 
         * Added hal_plf_eth_init() in order to initialise the Davicom
Index: packages/hal/arm/at91/at91sam7xek/current/cdl/hal_arm_at91sam7xek.cdl
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7xek/current/cdl/hal_arm_at91sam7xek.cdl,v
retrieving revision 1.3
diff -u -r1.3 hal_arm_at91sam7xek.cdl
--- packages/hal/arm/at91/at91sam7xek/current/cdl/hal_arm_at91sam7xek.cdl	5 Mar 2007 19:09:32 -0000	1.3
+++ packages/hal/arm/at91/at91sam7xek/current/cdl/hal_arm_at91sam7xek.cdl	30 Apr 2008 13:32:35 -0000
@@ -56,7 +56,8 @@
     compile       at91sam7xek_misc.c
     
     requires      { CYGHWR_HAL_ARM_AT91 == "AT91SAM7S" }
-    requires      { CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7x256" ||
+    requires      { CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7x512" || 
+                    CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7x256" ||
                     CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7x128" }
 		    
     requires      { is_active(CYGPKG_DEVS_ETH_PHY) implies
Index: packages/hal/arm/at91/at91sam7xek/current/src/at91sam7xek_misc.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7xek/current/src/at91sam7xek_misc.c,v
retrieving revision 1.2
diff -u -r1.2 at91sam7xek_misc.c
--- packages/hal/arm/at91/at91sam7xek/current/src/at91sam7xek_misc.c	5 Mar 2007 19:09:32 -0000	1.2
+++ packages/hal/arm/at91/at91sam7xek/current/src/at91sam7xek_misc.c	30 Apr 2008 13:23:25 -0000
@@ -97,7 +97,7 @@
 
    /* Power Down Mode */
    HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PB18, AT91_PIN_OUT);
-   HAL_ARM_AT91_GPIO_PUT(AT91_GPIO_PB19,0);
+   HAL_ARM_AT91_GPIO_PUT(AT91_GPIO_PB18,0);
 
    /* All the lines setup correctly. Now do a external reset and let the phy 
       start up in the correct mode */

[-- Attachment #3: mlt_arm_at91sam7x512_rom.ldi --]
[-- Type: application/octet-stream, Size: 1052 bytes --]

// eCos memory layout - Wed Apr 11 13:49:55 2001

// This is a generated file - do not edit

#include <cyg/infra/cyg_type.inc>
#include <pkgconf/hal_arm_at91sam7.h>

MEMORY
{
    ram : ORIGIN = 0x00200000, LENGTH = 0x20000
    rom : ORIGIN = 0x00100000, LENGTH = 0x80000
}

SECTIONS
{
    SECTIONS_BEGIN
    CYG_LABEL_DEFN(__reserved_bootmon) = 0x00000000; . = CYG_LABEL_DEFN(__reserved_bootmon) + 0x01000;
    SECTION_rom_vectors (rom, CYGNUM_HAL_ARM_AT91_IMAGE_ADDRESS, LMA_EQ_VMA)
    SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA)
    SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_fixed_vectors (ram, 0x00200040, LMA_EQ_VMA)
    SECTION_data (ram, ALIGN (0x4), FOLLOWING (.gcc_except_table))
    SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
    SECTIONS_END
}

[-- Attachment #4: mlt_arm_at91sam7x512_rom.h --]
[-- Type: application/octet-stream, Size: 914 bytes --]

// eCos memory layout - Wed Apr 11 13:49:55 2001

// This is a generated file - do not edit

#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>

#endif
#define CYGMEM_REGION_ram (0x00200000)
#define CYGMEM_REGION_ram_SIZE (0x20000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#define CYGMEM_REGION_rom (0x00100000)
#define CYGMEM_REGION_rom_SIZE (0x80000)
#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_bootmon) [];
#endif
#define CYGMEM_SECTION_reserved_bootmon (CYG_LABEL_NAME (__reserved_bootmon))
#define CYGMEM_SECTION_reserved_bootmon_SIZE (0x01000)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x00220000 - (size_t) CYG_LABEL_NAME (__heap1))

Re: Support for atsam7x512

[Andrew Lunn]

On Thu, May 01, 2008 at 07:17:58AM +0200, John Eigelaar wrote:
> Hi,
> 
> Here is a patch that adds all the CDL options and the necessary memory
> layout files to support 
> the Atmel at91sam7x512 as part of the at91sam7s HAL.

Thanks. I made one change to the patch. 

lunn@londo:~/eCos/work$ ecosconfig new at91sam7xek
U CYGHWR_HAL_ARM_AT91_FIQ, new inferred value 1
U CYGHWR_HAL_ARM_AT91, new inferred value AT91SAM7S
U CYGHWR_HAL_ARM_AT91SAM7, new inferred value at91sam7x512

As you had it, it infers a at91sam7x512 configuration, where as before
it was at91sam7x256. This changes the default behaviour and is likely
to trip somebody up. So i rearranged the CDL requires statements a
little so that at91sam7x256 remains the default.
 
Have you tested the flash driver? I think that also needs a patch. It
only supports up to 256K at the moment.

> Regards
> John Eigelaar
> 
> PS Any body know a way of incorporating the newly created files into the
> patch file ?

Not without having write access to the repository. Sorry.

    Andrew

RE: Support for atsam7x512

[John Eigelaar]

> -----Original Message-----
> From: Andrew Lunn [mailto:andrew@lunn.ch] 
> Sent: 01 May 2008 12:35 PM
> To: John Eigelaar
> Cc: ecos-patches@sourceware.org
> Subject: Re: Support for atsam7x512
> 
> 
> On Thu, May 01, 2008 at 07:17:58AM +0200, John Eigelaar wrote:
> > Hi,
> > 
> > Here is a patch that adds all the CDL options and the 
> necessary memory 
> > layout files to support the Atmel at91sam7x512 as part of the 
> > at91sam7s HAL.
> 
> Thanks. I made one change to the patch. 
> 
> lunn@londo:~/eCos/work$ ecosconfig new at91sam7xek
> U CYGHWR_HAL_ARM_AT91_FIQ, new inferred value 1
> U CYGHWR_HAL_ARM_AT91, new inferred value AT91SAM7S
> U CYGHWR_HAL_ARM_AT91SAM7, new inferred value at91sam7x512
> 
> As you had it, it infers a at91sam7x512 configuration, where 
> as before it was at91sam7x256. This changes the default 
> behaviour and is likely to trip somebody up. So i rearranged 
> the CDL requires statements a little so that at91sam7x256 
> remains the default.
>  
> Have you tested the flash driver? I think that also needs a 
> patch. It only supports up to 256K at the moment.

From the documentation I gather that the 512 has two EFC controllers,
The first one being an exact copy of the controller on the 256 and the 
second simarily controll the second block of 256K flash. I have not
tested
this yet but I presume the existing flash driver wil definitely need
some work
to enable the upper half of flash. 

> 
> > Regards
> > John Eigelaar
> > 
> > PS Any body know a way of incorporating the newly created 
> files into 
> > the patch file ?
> 
> Not without having write access to the repository. Sorry.
> 
>     Andrew
>