--- ChangeLog.orig	2007-07-12 15:19:33.000000000 +0200
+++ ChangeLog	2007-08-17 17:32:01.000000000 +0200
@@ -1,3 +1,8 @@
+2007-08-17  Hans Rosenfeld  <rosenfeld@grumpf.hope-2000.org>
+
+	* cdl/spi_lpc2xxx.cdl, src/spi_lpc2xxx.cxx: added option to set
+	  interrupt priorities
+
 2007-07-12  Hans Rosenfeld  <rosenfeld@grumpf.hope-2000.org>
 
 	* lpc2xxx: driver for on-chip SPI units
--- cdl/spi_lpc2xxx.cdl.orig	2007-07-12 15:48:46.000000000 +0200
+++ cdl/spi_lpc2xxx.cdl	2007-08-17 16:44:40.000000000 +0200
@@ -53,22 +53,46 @@
     parent      CYGPKG_IO_SPI
     active_if   CYGPKG_IO_SPI
 
+    requires    CYGPKG_ERROR
     include_dir cyg/io
     compile     spi_lpc2xxx.cxx
 
-    cdl_option CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS0 {
+    cdl_component CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS0 {
         display       "Enable SPI interface 0"
         flavor        bool
         default_value 1
         description   "The LPC2xxx controllers contain two SPI interfaces.
                        Enable this option to get support for SPI interface 0."
+
+        cdl_option CYGNUM_DEVS_SPI_ARM_LPC2XXX_BUS0_PRIO {
+            display       "Interrupt priority for SPI interface 0"
+            parent        CYGHWR_HAL_ARM_LPC2XXX_VIC
+            active_if     CYGHWR_HAL_ARM_LPC2XXX_VIC
+            flavor        data
+            default_value 1
+            legal_values  0 to 16
+            description   "The interrupt priority corresponds to the vector
+                           number in the Vectored Interrupt Controller. Lower
+                           numbers designate higher priorities."
+        }
     }
 
-    cdl_option CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS1 {
+    cdl_component CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS1 {
         display       "Enable SPI interface 1"
         flavor        bool
         default_value 1
         description   "The LPC2xxx controllers contain two SPI interfaces.
                        Enable this option to get support for SPI interface 1."
+        cdl_option CYGNUM_DEVS_SPI_ARM_LPC2XXX_BUS1_PRIO {
+            display       "Interrupt priority for SPI interface 1"
+            parent        CYGHWR_HAL_ARM_LPC2XXX_VIC
+            active_if     CYGHWR_HAL_ARM_LPC2XXX_VIC
+            flavor        data
+            default_value 2
+            legal_values  0 to 16
+            description   "The interrupt priority corresponds to the vector
+                           number in the Vectored Interrupt Controller. Lower
+                           numbers designate higher priorities."
+        }
     }
 }
\ No newline at end of file
--- src/spi_lpc2xxx.cxx.orig	2007-07-12 15:49:33.000000000 +0200
+++ src/spi_lpc2xxx.cxx	2007-08-17 15:09:37.000000000 +0200
@@ -303,7 +303,8 @@
  */
 void spi_lpc2xxx_init_bus(cyg_spi_lpc2xxx_bus_t *bus, 
                           cyg_addrword_t dev,
-                          cyg_vector_t vec)
+                          cyg_vector_t vec,
+                          cyg_priority_t prio)
 {
         bus->spi_bus.spi_transaction_begin    = spi_lpc2xxx_begin;
         bus->spi_bus.spi_transaction_transfer = spi_lpc2xxx_transfer;
@@ -319,7 +320,7 @@
         bus->spi_dev = (struct spi_dev *) dev;
         bus->spi_vect = vec;
         cyg_drv_interrupt_create(
-                vec, 0, (cyg_addrword_t) bus,
+                vec, prio, (cyg_addrword_t) bus,
                 &spi_lpc2xxx_isr, &spi_lpc2xxx_dsr,
                 &bus->spi_hand, &bus->spi_intr);
         cyg_drv_interrupt_attach(bus->spi_hand);
@@ -342,7 +343,8 @@
 
                 spi_lpc2xxx_init_bus(&cyg_spi_lpc2xxx_bus0,
                                      CYGARC_HAL_LPC2XXX_REG_SPI0_BASE,
-                                     CYGNUM_HAL_INTERRUPT_SPI0);
+                                     CYGNUM_HAL_INTERRUPT_SPI0,
+                                     CYGNUM_DEVS_SPI_ARM_LPC2XXX_BUS0_PRIO);
 #endif
 #ifdef CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS1
                 addr = CYGARC_HAL_LPC2XXX_REG_PIN_BASE
@@ -352,7 +354,8 @@
                 HAL_WRITE_UINT32(addr, tmp);
                 spi_lpc2xxx_init_bus(&cyg_spi_lpc2xxx_bus1,
                                      CYGARC_HAL_LPC2XXX_REG_SPI1_BASE,
-                                     CYGNUM_HAL_INTERRUPT_SPI1);
+                                     CYGNUM_HAL_INTERRUPT_SPI1,
+                                     CYGNUM_DEVS_SPI_ARM_LPC2XXX_BUS1_PRIO);
 #endif
         }
 };