* FR30 MB91301 cache support
@ 2008-09-19 11:34 Lars Poeschel
2008-09-19 17:29 ` Andrew Lunn
0 siblings, 1 reply; 4+ messages in thread
From: Lars Poeschel @ 2008-09-19 11:34 UTC (permalink / raw)
To: ecos-patches
[-- Attachment #1.1: Type: text/plain, Size: 174 bytes --]
Hello!
I created a patch that adds cache support to the mb91301 variant of
the fr30 architecture. The whole sram (4 kb) is used as an instruction
cache.
Regards,
Lars
[-- Attachment #1.2: cache.patch --]
[-- Type: application/octet-stream, Size: 11443 bytes --]
diff -rbBu ecos.export/packages/hal/fr30/arch/current/ChangeLog ecos.fr30/packages/hal/fr30/arch/current/ChangeLog
--- ecos.export/packages/hal/fr30/arch/current/ChangeLog 2008-07-11 19:59:26.000000000 +0200
+++ ecos.fr30/packages/hal/fr30/arch/current/ChangeLog 2008-09-19 11:56:47.000000000 +0200
@@ -1,3 +1,7 @@
+2008-09-19 Lars Poeschel <larsi@wh2.tu-dresden.de>
+
+ * include/hal_cache.h: Basic cache support
+
2008-07-01 Lars Poeschel <larsi@wh2.tu-dresden.de>
* src/vectors.S:
diff -rbBu ecos.export/packages/hal/fr30/arch/current/include/hal_cache.h ecos.fr30/packages/hal/fr30/arch/current/include/hal_cache.h
--- ecos.export/packages/hal/fr30/arch/current/include/hal_cache.h 2008-01-06 15:17:43.000000000 +0100
+++ ecos.fr30/packages/hal/fr30/arch/current/include/hal_cache.h 2008-09-19 11:56:46.000000000 +0200
@@ -46,81 +46,134 @@
//
// Author(s): larsi
// Contributors:
-// Date: 2007-07-09
+// Date: 2008-07-09
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
-// Usage:
-// #include <cyg/hal/hal_cache.h>
-// ...
+// Usage: #include <cyg/hal/hal_cache.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
-
+#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/var_cache.h>
+
//-----------------------------------------------------------------------------
// Cache dimensions
-// Data cache
-#define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
-#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
+// FR30 only has an instruction cache, so data cache macros are empty
+#ifndef HAL_DCACHE_SIZES_DEFINED
+#define HAL_DCACHE_SIZE 0 // Size of cache in bytes
+#define HAL_DCACHE_LINE_SIZE 16 // Size of a cache line
#define HAL_DCACHE_WAYS 2 // Associativity of the cache
-// Instruction cache
+#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
+#endif
+
+#ifndef HAL_ICACHE_SIZES_DEFINED
#define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
#define HAL_ICACHE_WAYS 2 // Associativity of the cache
-#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
-
+#endif
//-----------------------------------------------------------------------------
-// Global control of data cache
+// Global control of the data cache
+// FR30 only has an instruction cache, so data cache macros are empty
-// Enable the data cache
+// Enable the cache
+#ifndef HAL_DCACHE_ENABLE_DEFINED
#define HAL_DCACHE_ENABLE()
+#endif
-// Disable the data cache
+// Disable the cache
+#ifndef HAL_DCACHE_DISABLE_DEFINED
#define HAL_DCACHE_DISABLE()
+#endif
-// Query the state of the data cache
+// Query the state of the cache
+#ifndef HAL_DCACHE_IS_ENABLED_DEFINED
#define HAL_DCACHE_IS_ENABLED(_state_) \
CYG_MACRO_START \
_state_ = 1; \
CYG_MACRO_END
+#endif
// Invalidate the entire cache
+#ifndef HAL_DCACHE_INVALIDATE_ALL_DEFINED
#define HAL_DCACHE_INVALIDATE_ALL()
+#endif
-// Synchronize the contents of the cache with memory.
+// Synchronize the contents of the cache to the memory
+#ifndef HAL_DCACHE_SYNC_DEFINED
#define HAL_DCACHE_SYNC()
+#endif
+
+// Locks entry in the cache
+#ifndef HAL_DCACHE_LOCK_DEFINED
+#define HAL_DCACHE_LOCK(_base_, _size_)
+#endif
+
+// Unlocks entry in the cache
+#ifndef HAL_DCACHE_UNLOCK_DEFINED
+#define HAL_DCACHE_UNLOCK(_base_, _size_)
+#endif
+
+// Unlocks the whole cache.
+#ifndef HAL_DCACHE_UNLOCK_ALL_DEFINED
+#define HAL_DCACHE_UNLOCK_ALL()
+#endif
//-----------------------------------------------------------------------------
-// Global control of Instruction cache
+// Global control of the instruction cache
-// Enable the instruction cache
+// Enable the cache
+#ifndef HAL_ICACHE_ENABLE_DEFINED
#define HAL_ICACHE_ENABLE()
+#endif
-// Disable the instruction cache
+// Disable the cache
+#ifndef HAL_ICACHE_DISABLE_DEFINED
#define HAL_ICACHE_DISABLE()
+#endif
-// Query the state of the instruction cache
+// Query the state of the cache
+#ifndef HAL_ICACHE_IS_ENABLED_DEFINED
#define HAL_ICACHE_IS_ENABLED(_state_) \
CYG_MACRO_START \
_state_ = 1; \
CYG_MACRO_END
+#endif
// Invalidate the entire cache
+#ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED
#define HAL_ICACHE_INVALIDATE_ALL()
+#endif
-// Synchronize the contents of the cache with memory.
+// Synchronize the contents of the cache to the memory.
+#ifndef HAL_ICACHE_SYNC_DEFINED
#define HAL_ICACHE_SYNC()
+#endif
-//-----------------------------------------------------------------------------
-// Instruction cache line control
-
+// Locks entry in the cache, fr30 architecture does not support locking specifc
+// regions, so _base_ and _size are ignored and the whole cache is locked.
+// During cache lock only valid entries are locked. Invalid entries are updated.
+#ifndef HAL_ICACHE_LOCK_DEFINED
+#define HAL_ICACHE_LOCK(_base_, _size_)
+#endif
+
+// Unlocks entry in the cache. fr30 architecture does not support locking specifc
+// regions, so _base_ and _size are ignored and the whole cache is unlocked.
+#ifndef HAL_ICACHE_UNLOCK_DEFINED
+#define HAL_ICACHE_UNLOCK(_base_, _size_)
+#endif
+
+// Unlocks the whole cache.
+#ifndef HAL_ICACHE_UNLOCK_ALL_DEFINED
+#define HAL_ICACHE_UNLOCK_ALL()
+#endif
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_CACHE_H
Nur in ecos.fr30/packages/hal/fr30/arch/current/src: hal_syscall.c.
diff -rbBu ecos.export/packages/hal/fr30/mb91301/current/ChangeLog ecos.fr30/packages/hal/fr30/mb91301/current/ChangeLog
--- ecos.export/packages/hal/fr30/mb91301/current/ChangeLog 2008-07-11 20:00:23.000000000 +0200
+++ ecos.fr30/packages/hal/fr30/mb91301/current/ChangeLog 2008-09-19 11:56:47.000000000 +0200
@@ -1,3 +1,9 @@
+2008-09-19 Lars Poeschel <larsi@wh2.tu-dresden.de>
+
+ * include/variant.inc:
+ * include/var_cache.h: Support the cache of the mb91301 variant, uses it as
+ 4 kb instruction cache.
+
2008-07-01 Lars Poeschel <larsi@wh2.tu-dresden.de>
* src/fr30_md91301.ld: Reworked memory layout for flash support.
Nur in ecos.fr30/packages/hal/fr30/mb91301/current/include: var_cache.h.
diff -rbBu ecos.export/packages/hal/fr30/mb91301/current/include/variant.inc ecos.fr30/packages/hal/fr30/mb91301/current/include/variant.inc
--- ecos.export/packages/hal/fr30/mb91301/current/include/variant.inc 2008-07-11 20:00:23.000000000 +0200
+++ ecos.fr30/packages/hal/fr30/mb91301/current/include/variant.inc 2008-09-19 11:56:47.000000000 +0200
@@ -176,8 +176,11 @@
.equ FR30_MB91301_RTC_TMRLR, 0x50
.equ FR30_MB91301_RTC_TMR, 0x52
.equ FR30_MB91301_RTC_TMCSR, 0x56
-
-
+##-----------------------------------------------------------------------------
+## registers for cache settings
+##
+ .equ FR30_MB91301_CACHE_ISIZE, 0x307
+ .equ FR30_MB91301_CACHE_ICHCR, 0x3e7
##------------------------------------------------------------------------------
## CPU initialisation macro
@@ -337,5 +340,24 @@
#endif
#------------------------------------------------------------------------------
+# Cache initialization. We use 4 kb Cache, although not so documented.
+# The processor manual is not clear about this.
+# r0 and r1 are polluted
+
+#ifndef CYGPKG_HAL_FR30_CACHE_DEFINED
+#define CYGPKG_HAL_FR30_CACHE_DEFINED
+
+ .macro hal_cache_init
+
+ ldi:20 #FR30_MB91301_CACHE_ICHCR, r0
+# set (CYG_HAL_FR30_CACHE_ICHCR_RAM | CYG_HAL_FR30_CACHE_ICHCR_FLSH |
+# CYG_HAL_FR30_CACHE_ICHCR_ELKR | CYG_HAL_FR30_CACHE_ICHCR_ENAB)
+ ldi:20 #0x87, r1
+ stb r1, @r0
+ .endm
+
+#endif
+
+#------------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_VARIANT_INC
# end of variant.inc
diff -rbBu ecos.export/packages/hal/fr30/skmb91302/current/cdl/hal_fr30_skmb91302.cdl ecos.fr30/packages/hal/fr30/skmb91302/current/cdl/hal_fr30_skmb91302.cdl
--- ecos.export/packages/hal/fr30/skmb91302/current/cdl/hal_fr30_skmb91302.cdl 2008-01-06 15:17:43.000000000 +0100
+++ ecos.fr30/packages/hal/fr30/skmb91302/current/cdl/hal_fr30_skmb91302.cdl 2008-09-19 11:56:47.000000000 +0200
@@ -153,7 +153,7 @@
display "Global compiler flags"
flavor data
no_define
- default_value { "-Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -finit-priority -fomit-frame-pointer" }
+ default_value { "-Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fomit-frame-pointer -fno-use-cxa-atexit" }
description "This option controls the global compiler flags
which are used to compile all packages by default.
Individual packages may define options which
diff -rbBu ecos.export/packages/hal/fr30/skmb91302/current/ChangeLog ecos.fr30/packages/hal/fr30/skmb91302/current/ChangeLog
--- ecos.export/packages/hal/fr30/skmb91302/current/ChangeLog 2008-07-11 20:02:04.000000000 +0200
+++ ecos.fr30/packages/hal/fr30/skmb91302/current/ChangeLog 2008-09-19 11:56:47.000000000 +0200
@@ -1,3 +1,7 @@
+2008-09-19 Lars Poeschel <larsi@wh2.tu-dresden.de>
+
+ * include/plf_cache.h: Changed to the general arch-var-plf include scheme.
+
2008-07-01 Lars Poeschel <larsi@wh2.tu-dresden.de>
* src/platform.S: Startup routines for remapping the flash during
diff -rbBu ecos.export/packages/hal/fr30/skmb91302/current/include/plf_cache.h ecos.fr30/packages/hal/fr30/skmb91302/current/include/plf_cache.h
--- ecos.export/packages/hal/fr30/skmb91302/current/include/plf_cache.h 2008-01-06 15:17:43.000000000 +0100
+++ ecos.fr30/packages/hal/fr30/skmb91302/current/include/plf_cache.h 2008-09-19 11:56:47.000000000 +0200
@@ -44,26 +44,18 @@
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
-// Author(s): nickg
+// Author(s): Lars Poeschel
// Contributors:
-// Date: 2007-07-09
-// Purpose: Cache control API
+// Date: 2008-07-09
+// Purpose: Cache control API for skmb91302 platform
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
-// Usage:
-// #include <cyg/hal/plf_cache.h>
-// ...
-//
+// Usage: Included via "hal_cache.h". Do not use directly.
//
//####DESCRIPTIONEND####
//
//=============================================================================
-#include <pkgconf/hal.h>
-#include <cyg/infra/cyg_type.h>
-
-#include <cyg/hal/plf_cache.h>
-
//=============================================================================
// Nothing here at present.
[-- Attachment #1.3: Type: text/plain, Size: 1 bytes --]
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 194 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: FR30 MB91301 cache support
2008-09-19 11:34 FR30 MB91301 cache support Lars Poeschel
@ 2008-09-19 17:29 ` Andrew Lunn
2008-09-20 9:06 ` Lars Poeschel
0 siblings, 1 reply; 4+ messages in thread
From: Andrew Lunn @ 2008-09-19 17:29 UTC (permalink / raw)
To: Lars Poeschel; +Cc: ecos-patches
On Fri, Sep 19, 2008 at 01:33:52PM +0200, Lars Poeschel wrote:
> Hello!
>
> I created a patch that adds cache support to the mb91301 variant of the
> fr30 architecture. The whole sram (4 kb) is used as an instruction
> cache.
Hi Lars
lunn@londo:~/eCos/work$ rm -fr *
lunn@londo:~/eCos/work$ ecosconfig new skmb91302
lunn@londo:~/eCos/work$ ecosconfig tree
lunn@londo:~/eCos/work$ make -s
headers finished
In file included from /home/lunn/eCos/anoncvs-clean/packages/hal/fr30/skmb91302/current/src/plf_misc.c:65:
/home/lunn/eCos/work/install/include/cyg/hal/hal_cache.h:61:31: error: cyg/hal/var_cache.h: No such file or directory
make[1]: *** [src/plf_misc.o.d] Error 1
make: *** [build] Error 2
There is no variant hal to get the var_cache.h file from.
Have i done something wrong?
Andrew
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: FR30 MB91301 cache support
2008-09-19 17:29 ` Andrew Lunn
@ 2008-09-20 9:06 ` Lars Poeschel
2008-09-22 18:26 ` Andrew Lunn
0 siblings, 1 reply; 4+ messages in thread
From: Lars Poeschel @ 2008-09-20 9:06 UTC (permalink / raw)
To: ecos-patches; +Cc: Andrew Lunn
[-- Attachment #1.1: Type: text/plain, Size: 1149 bytes --]
Am Freitag, 19. September 2008 schrieb Andrew Lunn:
> On Fri, Sep 19, 2008 at 01:33:52PM +0200, Lars Poeschel wrote:
> > Hello!
> >
> > I created a patch that adds cache support to the mb91301 variant of the
> > fr30 architecture. The whole sram (4 kb) is used as an instruction
> > cache.
>
> Hi Lars
>
> lunn@londo:~/eCos/work$ rm -fr *
> lunn@londo:~/eCos/work$ ecosconfig new skmb91302
> lunn@londo:~/eCos/work$ ecosconfig tree
> lunn@londo:~/eCos/work$ make -s
> headers finished
> In file included from
> /home/lunn/eCos/anoncvs-clean/packages/hal/fr30/skmb91302/current/src/plf_m
>isc.c:65: /home/lunn/eCos/work/install/include/cyg/hal/hal_cache.h:61:31:
> error: cyg/hal/var_cache.h: No such file or directory make[1]: ***
> [src/plf_misc.o.d] Error 1
> make: *** [build] Error 2
>
> There is no variant hal to get the var_cache.h file from.
>
> Have i done something wrong?
No, you didn't do anything wrong. This was my mistake. I missed the
var_cache.h file, because I could not add it from my working copy to CVS.
Sorry!
Here it is. It goes to packages/hal/fr30/current/mb91031/include obviously.
Lars
[-- Attachment #1.2: var_cache.h --]
[-- Type: text/x-chdr, Size: 8112 bytes --]
#ifndef CYGONCE_VAR_CACHE_H
#define CYGONCE_VAR_CACHE_H
//=============================================================================
//
// var_cache.h
//
// VAR cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2007 eCosCentric Ltd.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): Lars Poeschel
// Contributors:
// Date: 2008-07-09
// Purpose: Cache control API for mb91301 variant
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
// Usage: Included via "hal_cache.h". Do not use directly.
//
//####DESCRIPTIONEND####
//
//=============================================================================
#include <cyg/hal/plf_cache.h>
//-----------------------------------------------------------------------------
// Cache configuration registers
#define CYG_HAL_FR30_CACHE_ISIZE 0x307
#define CYG_HAL_FR30_CACHE_ICHCR 0x3e7
#define CYG_HAL_FR30_CACHE_ICHCR_RAM 0x80
#define CYG_HAL_FR30_CACHE_ICHCR_GBLK 0x20
#define CYG_HAL_FR30_CACHE_ICHCR_ALFL 0x10
#define CYG_HAL_FR30_CACHE_ICHCR_EOLK 0x08
#define CYG_HAL_FR30_CACHE_ICHCR_ELKR 0x04
#define CYG_HAL_FR30_CACHE_ICHCR_FLSH 0x02
#define CYG_HAL_FR30_CACHE_ICHCR_ENAB 0x01
//-----------------------------------------------------------------------------
// Cache dimensions
// Unified cache (in reality it is only an instruction cache)
#define HAL_ICACHE_SIZES_DEFINED
#define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
#define HAL_ICACHE_WAYS 2 // Associativity of the cache
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
//-----------------------------------------------------------------------------
// Global control of the cache
// Enable the cache
// This is setting the RAM, ELKR, FLSH and ENAB bits in ICHCR
#ifndef HAL_ICACHE_ENABLE_DEFINED
#define HAL_ICACHE_ENABLE_DEFINED
#define HAL_ICACHE_ENABLE() \
CYG_MACRO_START \
HAL_WRITE_UINT8(CYG_HAL_FR30_CACHE_ICHCR, \
CYG_HAL_FR30_CACHE_ICHCR_RAM | CYG_HAL_FR30_CACHE_ICHCR_ELKR | \
CYG_HAL_FR30_CACHE_ICHCR_FLSH | CYG_HAL_FR30_CACHE_ICHCR_ENAB) \
CYG_MACRO_END
#endif
// Disable the cache
// This is clearing the ENAB bit in ICHCR
#ifndef HAL_ICACHE_DISABLE_DEFINED
#define HAL_ICACHE_DISABLE_DEFINED
#define HAL_ICACHE_DISABLE() \
CYG_MACRO_START \
HAL_WRITE_UINT8(CYG_HAL_FR30_CACHE_ICHCR, \
CYG_HAL_FR30_CACHE_ICHCR_RAM | CYG_HAL_FR30_CACHE_ICHCR_FLSH) \
CYG_MACRO_END
#endif
// Query the state of the cache
// read ICHCR, when enabled bit0 should be 1, else 0
#ifndef HAL_ICACHE_IS_ENABLED_DEFINED
#define HAL_ICACHE_IS_ENABLED_DEFINED
#define HAL_ICACHE_IS_ENABLED(_state_) \
CYG_MACRO_START \
HAL_READ_UINT8(CYG_HAL_FR30_CACHE_ICHCR, _state_) \
_state_ &= 0x01; \
CYG_MACRO_END
#endif
// Invalidate the entire cache
// The processor manual is not clear about this. I clear the valid bit and the
// subblock valid bits of each subblock in all 128 tags of all 2 ways.
#ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED
#define HAL_ICACHE_INVALIDATE_ALL_DEFINED
#define HAL_ICACHE_INVALIDATE_ALL() \
CYG_MACRO_START \
int _i_; \
for(_i_ = 0x10000; _i_ < 0x10800; _i_ += 0x10) { \
HAL_WRITE_UINT32(_i_, 0x00000000); \
HAL_WRITE_UINT32(_i_ + 0x4000, 0x00000000); \
} \
CYG_MACRO_END
#endif
// Synchronize the contents of the cache to the memory.(flush)
#ifndef HAL_ICACHE_SYNC_DEFINED
#define HAL_ICACHE_SYNC_DEFINED
#define HAL_ICACHE_SYNC() \
CYG_MACRO_START \
cyg_uint8 _value_; \
HAL_READ_UINT8(CYG_HAL_FR30_CACHE_ICHCR, _value_); \
HAL_WRITE_UINT8(CYG_HAL_FR30_CACHE_ICHCR, \
_value_ | CYG_HAL_FR30_CACHE_ICHCR_FLSH); \
CYG_MACRO_END
#endif
// Locks entry in the cache, fr30 architecture does not support locking specifc
// regions. It is only possible to lock specific entries in the cache. This
// seems not to match ecos understanding of cache locking, so _base_ and _size_
// are ignored and the whole cache is locked.
// During cache lock only valid entries are locked. Invalid entries are updated.
#ifndef HAL_ICACHE_LOCK_DEFINED
#define HAL_ICACHE_LOCK_DEFINED
#define HAL_ICACHE_LOCK(_base_, _size_) \
CYG_MACRO_START \
CYG_UINT8 _value_; \
HAL_READ_UINT8(CYG_HAL_FR30_CACHE_ICHCR, _value_); \
HAL_WRITE_UINT8(CYG_HAL_FR30_CACHE_ICHCR, \
_value_ | CYG_HAL_FR30_CACHE_ICHCR_GBLK); \
CYG_MACRO_END
#endif
// Unlocks entry in the cache. fr30 architecture does not support locking specifc
// regions, so _base_ and _size are ignored and the whole cache is unlocked.
#ifndef HAL_ICACHE_UNLOCK_DEFINED
#define HAL_ICACHE_UNLOCK_DEFINED
#define HAL_ICACHE_UNLOCK(_base_, _size_) \
CYG_MACRO_START \
cyg_uint8 _value_; \
HAL_READ_UINT8(CYG_HAL_FR30_CACHE_ICHCR, _value_); \
HAL_WRITE_UINT8(CYG_HAL_FR30_CACHE_ICHCR, \
_value_ & ~CYG_HAL_FR30_CACHE_ICHCR_GBLK); \
CYG_MACRO_END
#endif
// Unlocks the whole cache. This is the same as HAL_ICACHE_UNLOCK
#ifndef HAL_ICACHE_UNLOCK_ALL_DEFINED
#define HAL_ICACHE_UNLOCK_ALL_DEFINED
#define HAL_ICACHE_UNLOCK_ALL() HAL_ICACHE_UNLOCK(0, 0)
#endif
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_VAR_CACHE_H
// End of Val_cache.h
[-- Attachment #2: This is a digitally signed message part. --]
[-- Type: application/pgp-signature, Size: 197 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: FR30 MB91301 cache support
2008-09-20 9:06 ` Lars Poeschel
@ 2008-09-22 18:26 ` Andrew Lunn
0 siblings, 0 replies; 4+ messages in thread
From: Andrew Lunn @ 2008-09-22 18:26 UTC (permalink / raw)
To: Lars Poeschel; +Cc: ecos-patches
> No, you didn't do anything wrong. This was my mistake. I missed the
> var_cache.h file, because I could not add it from my working copy to CVS.
> Sorry!
> Here it is. It goes to packages/hal/fr30/current/mb91031/include obviously.
Thanks
I committed everything now.
Andrew
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2008-09-22 18:26 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2008-09-19 11:34 FR30 MB91301 cache support Lars Poeschel
2008-09-19 17:29 ` Andrew Lunn
2008-09-20 9:06 ` Lars Poeschel
2008-09-22 18:26 ` Andrew Lunn
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).