[Bug 1001186] Introduce Cortex-M4 to the Cortex-M architecture

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Nick Garnett <nickg@ecoscentric.com> changed:

           What    |Removed                     |Added
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                 CC|                            |nickg@ecoscentric.com

--- Comment #3 from Nick Garnett <nickg@ecoscentric.com> 2011-04-06 14:15:25 BST ---
The M4 stuff looks OK to me.

However, I am not sure that we need the M0 option. The v6-M architecture is a
severely cut down version of the v7-M architecture. It lacks a lot of the
features we currently use in the Cortex-M HAL. Things like the dual stack
pointers, SVC, PendSVC and SysTick are only available if the OS option is
enabled. Other things like the programmable vector table base address and the
BASEPRI register are entirely absent.

Adding M0 to the list would raise entirely false expectations that this
processor type was supported. In fact, I would prefer to remove M1, since these
parts have the same problems.

We would have to do quite a lot of work to support M0/1. Given that these parts
are targeted at very low resource systems, I doubt that there will ever be much
demand for eCos on these.

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