From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 10164 invoked by alias); 17 Aug 2011 20:26:12 -0000 Received: (qmail 10138 invoked by uid 22791); 17 Aug 2011 20:26:10 -0000 X-SWARE-Spam-Status: No, hits=-1.9 required=5.0 tests=AWL,BAYES_00 X-Spam-Check-By: sourceware.org Received: from hagrid.ecoscentric.com (HELO mail.ecoscentric.com) (212.13.207.197) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 17 Aug 2011 20:25:55 +0000 Received: from localhost (hagrid.ecoscentric.com [127.0.0.1]) by mail.ecoscentric.com (Postfix) with ESMTP id 7623F2F78014 for ; Wed, 17 Aug 2011 21:25:54 +0100 (BST) Received: from mail.ecoscentric.com ([127.0.0.1]) by localhost (hagrid.ecoscentric.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pXpH1WW4U-nu; Wed, 17 Aug 2011 21:25:52 +0100 (BST) From: bugzilla-daemon@bugs.ecos.sourceware.org To: ecos-patches@ecos.sourceware.org Subject: [Bug 1001275] Cortex-M (armV7) architecture endian instructions / Applied on lwIP X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: eCos X-Bugzilla-Component: Patches and contributions X-Bugzilla-Keywords: X-Bugzilla-Severity: enhancement X-Bugzilla-Who: ilijak@siva.com.mk X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Priority: low X-Bugzilla-Assigned-To: unassigned@bugs.ecos.sourceware.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Changed-Fields: In-Reply-To: References: X-Bugzilla-URL: http://bugs.ecos.sourceware.org/ Auto-Submitted: auto-generated Content-Type: text/plain; charset="UTF-8" MIME-Version: 1.0 Date: Wed, 17 Aug 2011 20:26:00 -0000 Message-Id: <20110817202552.894F92F78010@mail.ecoscentric.com> Mailing-List: contact ecos-patches-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: ecos-patches-owner@ecos.sourceware.org X-SW-Source: 2011-08/txt/msg00004.txt.bz2 Please do not reply to this email. Use the web interface provided at: http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001275 --- Comment #3 from Ilija Kocho 2011-08-17 21:25:47 BST --- Hi Sergei, thank you for comments. (In reply to comment #2) > Hi Ijlija, > > Thank you for your attention to low-memory footprint eCos targets and your > ideas around, i.e. how to utilize every bit on such CPUs :-) And spare some clock cycles :) > > My $.02. > > Instead hal_arch_instr.h I would create _regs.h header file to define > a few instructions in assembler. In your case it is cortexm_regs.h. > > NOTE: There are the precendents of such definitions in other architecture > trees. > Right! Actually I was looking for such a header but obviously not hard enough. I would have been happier if file name was hal_regs.h, but let's not break the habit, and use cortexm_regs.h > I mean (snippets not tested!) > > #ifndef CYGONCE_HAL_CORTEXM_REGS_H > #define CYGONCE_HAL_CORTEXM_REGS_H > //==================================================== ... > // > // cortexm_regs.h > // > // Cortex-M CPU definitions > // > // ... > > #include > > #include > > // Macro to embed rev instructions in C code > #define CYGARC_REV(_origin_, _swapped_) \ > asm volatile( "rev %0, %1\n" \ > : "=r" (_swapped_) \ > : "r" (_origin_) \ > ); > > #define CYGARC_REV16(_origin_, _swapped_) \ > asm volatile( "rev16 %0, %1\n" \ > : "=r" (_swapped_) \ > : "r" (_origin_) \ > ); // We could also define the functions, now using macros. // In context with this please look at discussion // regarding lwIP below. // Regarding functions I have one dillema: // Could we rename cygarc_arm_rev*() functions into cygarc_byteswap*()? #define CYGARC_HAL_INSTR_ATTR \ __externC __attribute__(( always_inline )) inline // This is an optional name for cygarc_arm_rev() // CYGARC_HAL_INSTR_ATTR cyg_uint32 cygarc_byteswap(cyg_uint32 original){ CYGARC_HAL_INSTR_ATTR cyg_uint32 cygarc_arm_rev(cyg_uint32 original){ cyg_uint32 swapped; CYGARC_REV(swapped, original); return swapped; } CYGARC_HAL_INSTR_ATTR cyg_uint32 cygarc_arm_rev16(cyg_uint32 original){ cyg_uint32 swapped; CYGARC_REV16(swapped, original); return swapped; } CYGARC_HAL_INSTR_ATTR cyg_int32 cygarc_arm_revsh(cyg_int32 original){ cyg_int32 swapped; CYGARC_REVSH(swapped, original); return swapped; } // Platform supports endian operations. #define CYGARC_BYTESWAP 1 #define CYGARC_BYTESWAP32(__val) cygarc_arm_rev(__val) #define CYGARC_BYTESWAP16(__val) ((cyg_uint16)cygarc_arm_rev16(__val)) > // ---------------------------------------------------- ... > // End of cortexm_regs.h > #endif // ifdef CYGONCE_HAL_CORTEXM_REGS_H > > > And then I would add only needed inline functions and declarations in some > header file (again, not tested) > > #include > > #define LWIP_PLATFORM_HTONL( _hostlong_ ) hal_htol( _hostlong_ ) > #define LWIP_PLATFORM_HTONS( _hostshort_ ) hal_htos( _hostshort_ ) I think that it wouldn't be appropriate to use ARM-related mnemonics (CYGARC_REV) in lwIP subtree. Also we should avoid, putting lwIP - related names into HAL. For this reason I have defined CYGARC_BUTESWAPxx() - architecture neutral macro name that could be used in other architectures as appropriate. > > static inline cyg_uint32 hal_htonl(cyg_uint32 hostslong) > { > cyg_uint32 netlong; > CYGARC_REV(hostlong, netlong); > return netlong; > } > > static inline cyg_uint16 hal_htons(cyg_uint16 hostshort) > { > cyg_uint16 netshort; > CYGARC_REV16(hostshort, netshort); > return netshort; > } > > > But, I would resist to put them in hal_arch.h ... And it is mine only. By > other hand lwipopts.h includes that header only. I thought it's pitty that we > have hal_io.h, but not hal_net.h. Thus, we need more expert views on code's > arrangement. I think that hal_arch.h isn't bad, after all cortexm_regs.h belong to hal and is architecture specific. I am not able to run the code at present but it builds without warnings. Disassembly looks as expected. Ilija -- Configure bugmail: http://bugs.ecos.sourceware.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are on the CC list for the bug.