From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 3917 invoked by alias); 23 Aug 2011 19:27:58 -0000 Received: (qmail 3906 invoked by uid 22791); 23 Aug 2011 19:27:58 -0000 X-SWARE-Spam-Status: No, hits=-1.9 required=5.0 tests=AWL,BAYES_00 X-Spam-Check-By: sourceware.org Received: from hagrid.ecoscentric.com (HELO mail.ecoscentric.com) (212.13.207.197) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 23 Aug 2011 19:27:44 +0000 Received: from localhost (hagrid.ecoscentric.com [127.0.0.1]) by mail.ecoscentric.com (Postfix) with ESMTP id 1748A2F7800E for ; Tue, 23 Aug 2011 20:27:43 +0100 (BST) Received: from mail.ecoscentric.com ([127.0.0.1]) by localhost (hagrid.ecoscentric.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Zw2VFhphsQmN; Tue, 23 Aug 2011 20:27:41 +0100 (BST) From: bugzilla-daemon@bugs.ecos.sourceware.org To: ecos-patches@ecos.sourceware.org Subject: [Bug 1001275] Cortex-M (armV7) architecture endian instructions / Applied on lwIP X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: eCos X-Bugzilla-Component: Patches and contributions X-Bugzilla-Keywords: X-Bugzilla-Severity: enhancement X-Bugzilla-Who: sergei.gavrikov@gmail.com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Priority: low X-Bugzilla-Assigned-To: unassigned@bugs.ecos.sourceware.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Changed-Fields: In-Reply-To: References: X-Bugzilla-URL: http://bugs.ecos.sourceware.org/ Auto-Submitted: auto-generated Content-Type: text/plain; charset="UTF-8" MIME-Version: 1.0 Date: Tue, 23 Aug 2011 19:27:00 -0000 Message-Id: <20110823192741.8666A2F78004@mail.ecoscentric.com> Mailing-List: contact ecos-patches-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: ecos-patches-owner@ecos.sourceware.org X-SW-Source: 2011-08/txt/msg00024.txt.bz2 Please do not reply to this email. Use the web interface provided at: http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001275 --- Comment #23 from Sergei Gavrikov 2011-08-23 20:27:36 BST --- (In reply to comment #19) > Created an attachment (id=1348) --> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1348) > Cortex-M architecture endian 110823 > > Here I re-submit Cortex-M arch integral patch, headers+CDL. Regarding attachment 1348 hal_cortexm.cdl (CYGIMP_HAL_ARCH_ENDIAN): reformatted according CDL coding style, fixed a typo in description (s/bute/byte) and I would have said + default_value 1 + description " + Cortex-M architecture implements instructions for endian + manipulation (byte swapping). If enabled, this feature + can produce shorter and faster code for that." cortexm_regs.h: Ilija, I missed that you have used such an order for arguments in REV macros, for example +// Reverse word +#define CYGARC_REV(_swapped_,_original_) \ + __asm__ volatile ("rev %0, %1\n" : "=r"(_swapped_) : "r"(_original_)) + It looks clear for ARM assembler gurus (dst <- src), and for C-guys it looks a bit puzzled, (IMO) they are accustomed to same #define HAL_READ_UINT32( _register_, _value_ ) \ Still, I would use prototypes where result returns in the second argument. And if you have no objections I would use multiline variants for those macros. #define CYGARC_REV( _origin_, _swapped_ ) \ asm volatile( "rev %0, %1\n" \ : "=r" (_swapped_) \ : "r" (_origin_) \ ); You will not be against it (re-ordering the arguments)? -- Configure bugmail: http://bugs.ecos.sourceware.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are on the CC list for the bug.