From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 23991 invoked by alias); 11 Oct 2011 21:45:13 -0000 Received: (qmail 23955 invoked by uid 22791); 11 Oct 2011 21:45:10 -0000 X-SWARE-Spam-Status: No, hits=-1.9 required=5.0 tests=AWL,BAYES_00 X-Spam-Check-By: sourceware.org Received: from hagrid.ecoscentric.com (HELO mail.ecoscentric.com) (212.13.207.197) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 11 Oct 2011 21:44:44 +0000 Received: from localhost (hagrid.ecoscentric.com [127.0.0.1]) by mail.ecoscentric.com (Postfix) with ESMTP id 62C6C2F78010 for ; Tue, 11 Oct 2011 22:44:43 +0100 (BST) Received: from mail.ecoscentric.com ([127.0.0.1]) by localhost (hagrid.ecoscentric.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 36VR-0TvDrK7; Tue, 11 Oct 2011 22:44:38 +0100 (BST) From: bugzilla-daemon@bugs.ecos.sourceware.org To: ecos-patches@ecos.sourceware.org Subject: [Bug 1001219] Ethernet driver for STM32 connectivity line with port on MMstm32f107 board. X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: eCos X-Bugzilla-Component: Patches and contributions X-Bugzilla-Keywords: X-Bugzilla-Severity: enhancement X-Bugzilla-Who: jerzdy@gmail.com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Priority: low X-Bugzilla-Assigned-To: unassigned@bugs.ecos.sourceware.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Changed-Fields: In-Reply-To: References: X-Bugzilla-URL: http://bugs.ecos.sourceware.org/ Auto-Submitted: auto-generated Content-Type: text/plain; charset="UTF-8" MIME-Version: 1.0 Date: Tue, 11 Oct 2011 21:45:00 -0000 Message-Id: <20111011214438.8C47F2F78001@mail.ecoscentric.com> Mailing-List: contact ecos-patches-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: ecos-patches-owner@ecos.sourceware.org X-SW-Source: 2011-10/txt/msg00022.txt.bz2 Please do not reply to this email. Use the web interface provided at: http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001219 --- Comment #13 from Jerzy Dyrda 2011-10-11 22:44:36 BST --- (In reply to comment #11) > (In reply to comment #7) > > Created an attachment (id=1396) --> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1396) [details] [details] > > Variant modification needed by STM32 CL > > http://bugs.ecos.sourceware.org/attachment.cgi?id=1396&action=diff#ecos_clear/packages/hal/cortexm/stm32/var/current/include/var_io.h_sec7 > > Ethernet definitions are usually stored with Ethernet driver, either with C > source or in a header file (I prefer the second). If you move it there than > that would imply that names do not contain "_HAL_". I would like to follow convention e.g. ADC registers with pin description are stored in this header. I thought that any new peripheral description will be stored in var_io.h > > http://bugs.ecos.sourceware.org/attachment.cgi?id=1396&action=diff#ecos_clear/packages/hal/cortexm/stm32/var/current/src/hal_diag.c_sec1 > > What is the reason for renaming of hal_stm32_serial_init() into > hal_stm32_serial_init_channel() I'm not sure now :) but as I suppose it doesn't work. BTW. Definition of function is static void hal_stm32_serial_init(void) but function is called with argument &stm32_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] IMHO in case of non virtual vector is initialized other serial port than I expect > > http://bugs.ecos.sourceware.org/attachment.cgi?id=1396&action=diff#ecos_clear/packages/hal/cortexm/stm32/var/current/src/stm32_misc.c_sec2 > > Changes like this may look attractive but (as well as previous one) may (will) > break other user's applications. Conditional compilation may help but in this > case I suggest to keep old code, it's simple and provides working conditions > to all peripherals. I agree I have just added it because in case of non virtual vector isn't such function. > http://bugs.ecos.sourceware.org/attachment.cgi?id=1396&action=diff#ecos_clear/packages/hal/cortexm/stm32/var/current/src/stm32_misc.c_sec3 > > Is this necessary? Yes RCC (clock generation) module for CL has another PLL stage which is required to achieve proper clock for eth module. BTW I have further bad news : in STM32F2xx family RCC module is different than STM32f105/7 family. > > http://bugs.ecos.sourceware.org/attachment.cgi?id=1396&action=diff#ecos_clear/packages/hal/cortexm/stm32/var/current/src/stm32_misc.c_sec4 > > I'm referring to following: > - hal_stm32_sysclk /= 2; > + hal_stm32_sysclk = CYGARC_HAL_CORTEXM_STM32_INTERNAL_CLOCK / 2; > > If it works don't fix it :) It was made assumption that internal clock is the same as input clock but it's wrong for CL controller. > Now some minor remarks: > Comments like > #endif // CYGINT_HAL_CORTEXM_STM32_CL>0 > on some places are not consistent with their respective #ifs. > And: (this is my personal only) > #if CYGINT_HAL_CORTEXM_STM32_CL != 0 > or > #if CYGINT_HAL_CORTEXM_STM32_CL > is more common than >0. OK I check it. -- Configure bugmail: http://bugs.ecos.sourceware.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are on the CC list for the bug.