From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28240 invoked by alias); 4 May 2010 12:27:33 -0000 Received: (qmail 28225 invoked by uid 22791); 4 May 2010 12:27:29 -0000 X-SWARE-Spam-Status: No, hits=-1.4 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,UPPERCASE_50_75 X-Spam-Check-By: sourceware.org Received: from relay.ptn-ipout02.plus.net (HELO relay.ptn-ipout02.plus.net) (212.159.7.36) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 04 May 2010 12:27:22 +0000 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: ApsEAH+v30vUnwpB/2dsb2JhbACeIrs0hRME Received: from mailc01.plus.net (HELO pih-smtp-proxy01.plus.net) ([212.159.10.65]) by relay.ptn-ipout02.plus.net with ESMTP; 04 May 2010 13:27:20 +0100 Received: from [80.189.249.164] (helo=[192.168.0.2]) by pih-smtp-proxy01.plus.net with esmtp (Exim 4.63) (envelope-from ) id 1O9HDb-0000ep-Uz for ecos-patches@ecos.sourceware.org; Tue, 04 May 2010 13:27:20 +0100 Received: from 127.0.0.1 (AVG SMTP 9.0.814 [271.1.1/2852]); Tue, 04 May 2010 13:27:28 +0100 Message-ID: <4BE012B0.70202@spen-soft.co.uk> Date: Tue, 04 May 2010 12:27:00 -0000 From: Spencer Oliver User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.1.9) Gecko/20100317 Lightning/1.0b1 Thunderbird/3.0.4 MIME-Version: 1.0 To: ecos-patches@ecos.sourceware.org Subject: [PATCH] stm32 uart: use 16bit register access Content-Type: multipart/mixed; boundary="------------060901010905020303040904" X-IsSubscribed: yes Mailing-List: contact ecos-patches-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: ecos-patches-owner@ecos.sourceware.org X-SW-Source: 2010-05/txt/msg00003.txt.bz2 This is a multi-part message in MIME format. --------------060901010905020303040904 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-length: 104 stm32 uart: use 16bit register access Access all uart register using 16bit access, as per the ST docs. --------------060901010905020303040904 Content-Type: text/plain; name="ecos.hg_rev2949.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="ecos.hg_rev2949.patch" Content-length: 9457 # HG changeset patch # User Spencer Oliver # Date 1272975594 -3600 # Node ID c88d9f19de1aa679335bbec8b609e824d1fbd015 # Parent d31e3aac03a66dd841d6b9a48c1261c00b437475 stm32 uart: use 16bit register access Access all uart register using 16bit access, as per the ST docs. diff -r d31e3aac03a6 -r c88d9f19de1a packages/devs/serial/cortexm/stm32/current/src/stm32_serial.c --- a/packages/devs/serial/cortexm/stm32/current/src/stm32_serial.c Tue May 04 13:18:19 2010 +0100 +++ b/packages/devs/serial/cortexm/stm32/current/src/stm32_serial.c Tue May 04 13:19:54 2010 +0100 @@ -436,15 +436,15 @@ cr1 |= CYGHWR_HAL_STM32_UART_CR1_TE | CYGHWR_HAL_STM32_UART_CR1_RE; - HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); - HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR2, cr2 ); + HAL_WRITE_UINT16( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); + HAL_WRITE_UINT16( base+CYGHWR_HAL_STM32_UART_CR2, cr2 ); // Set up baud rate hal_stm32_uart_setbaud( base, select_baud[new_config->baud] ); // Enable the uart cr1 |= CYGHWR_HAL_STM32_UART_CR1_UE; - HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); + HAL_WRITE_UINT16( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); #ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_HW @@ -462,10 +462,10 @@ cr1 |= CYGHWR_HAL_STM32_UART_CR1_RXNEIE; cr3 |= CYGHWR_HAL_STM32_UART_CR3_EIE; - HAL_WRITE_UINT32( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); + HAL_WRITE_UINT16( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); } - HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR3, cr3 ); + HAL_WRITE_UINT16( base+CYGHWR_HAL_STM32_UART_CR3, cr3 ); stm32_chan->tx_active = false; @@ -528,11 +528,11 @@ const CYG_ADDRWORD base = stm32_chan->base; cyg_uint32 status; - HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_SR, status ); + HAL_READ_UINT16( base + CYGHWR_HAL_STM32_UART_SR, status ); if (status & CYGHWR_HAL_STM32_UART_SR_TXE) { - HAL_WRITE_UINT32( base + CYGHWR_HAL_STM32_UART_DR, c ); + HAL_WRITE_UINT16( base + CYGHWR_HAL_STM32_UART_DR, c ); return true; } @@ -549,10 +549,10 @@ cyg_uint32 status; do { - HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_SR, status ); + HAL_READ_UINT16( base + CYGHWR_HAL_STM32_UART_SR, status ); } while ((status & CYGHWR_HAL_STM32_UART_SR_TXE) == 0); - HAL_WRITE_UINT32( base + CYGHWR_HAL_STM32_UART_DR, c ); + HAL_WRITE_UINT16( base + CYGHWR_HAL_STM32_UART_DR, c ); return true; } @@ -568,7 +568,7 @@ CYG_WORD32 c; // Read data - HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_DR, c); + HAL_READ_UINT16( base + CYGHWR_HAL_STM32_UART_DR, c); return (unsigned char) (c&0xFF); } @@ -583,10 +583,10 @@ cyg_uint32 c; do { - HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_SR, stat ); + HAL_READ_UINT16( base + CYGHWR_HAL_STM32_UART_SR, stat ); } while ((stat & CYGHWR_HAL_STM32_UART_SR_RXNE) == 0); - HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_DR, c); + HAL_READ_UINT16( base + CYGHWR_HAL_STM32_UART_DR, c); return (unsigned char) (c&0xFF); } @@ -686,9 +686,9 @@ if( !stm32_chan->tx_active ) { stm32_chan->tx_active = true; - HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); + HAL_READ_UINT16( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); cr1 |= CYGHWR_HAL_STM32_UART_CR1_TXEIE; - HAL_WRITE_UINT32( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); + HAL_WRITE_UINT16( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); } } @@ -706,9 +706,9 @@ if( stm32_chan->tx_active ) { stm32_chan->tx_active = false; - HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); + HAL_READ_UINT16( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); cr1 &= ~CYGHWR_HAL_STM32_UART_CR1_TXEIE; - HAL_WRITE_UINT32( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); + HAL_WRITE_UINT16( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); } } @@ -739,7 +739,7 @@ cyg_uint32 ret = CYG_ISR_HANDLED; cyg_drv_interrupt_acknowledge(vector); - HAL_READ_UINT32(base + CYGHWR_HAL_STM32_UART_SR, stat); + HAL_READ_UINT16(base + CYGHWR_HAL_STM32_UART_SR, stat); if( stat & CYGHWR_HAL_STM32_UART_SR_RXNE ) { @@ -751,7 +751,7 @@ if( next == STM32_RXBUFSIZE ) next = 0; - HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_DR, c); + HAL_READ_UINT16( base + CYGHWR_HAL_STM32_UART_DR, c); if( next != stm32_chan->buf_tail ) { @@ -764,15 +764,15 @@ // TODO: deal with buffer overflow } - HAL_READ_UINT32(base + CYGHWR_HAL_STM32_UART_SR, stat); + HAL_READ_UINT16(base + CYGHWR_HAL_STM32_UART_SR, stat); } } else if( stat & CYGHWR_HAL_STM32_UART_SR_TXE ) { cyg_uint32 cr1; - HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); + HAL_READ_UINT16( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); cr1 &= ~CYGHWR_HAL_STM32_UART_CR1_TXEIE; - HAL_WRITE_UINT32( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); + HAL_WRITE_UINT16( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); ret |= CYG_ISR_CALL_DSR; } @@ -782,7 +782,7 @@ { // Clear CTS status if we see it. stat &= ~CYGHWR_HAL_STM32_UART_SR_CTS; - HAL_WRITE_UINT32( base + CYGHWR_HAL_STM32_UART_SR, stat ); + HAL_WRITE_UINT16( base + CYGHWR_HAL_STM32_UART_SR, stat ); } if( stat & (CYGHWR_HAL_STM32_UART_SR_FE|CYGHWR_HAL_STM32_UART_SR_NE|CYGHWR_HAL_STM32_UART_SR_ORE) ) @@ -816,7 +816,7 @@ (chan->callbacks->rcv_char)(chan, c); } - HAL_READ_UINT32(base + CYGHWR_HAL_STM32_UART_SR, stat); + HAL_READ_UINT16(base + CYGHWR_HAL_STM32_UART_SR, stat); if( stm32_chan->tx_active && stat & CYGHWR_HAL_STM32_UART_SR_TXE ) { @@ -826,9 +826,9 @@ if( stm32_chan->tx_active ) { - HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); + HAL_READ_UINT16( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); cr1 |= CYGHWR_HAL_STM32_UART_CR1_TXEIE; - HAL_WRITE_UINT32( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); + HAL_WRITE_UINT16( base + CYGHWR_HAL_STM32_UART_CR1, cr1 ); } } } diff -r d31e3aac03a6 -r c88d9f19de1a packages/hal/cortexm/stm32/var/current/src/hal_diag.c --- a/packages/hal/cortexm/stm32/var/current/src/hal_diag.c Tue May 04 13:18:19 2010 +0100 +++ b/packages/hal/cortexm/stm32/var/current/src/hal_diag.c Tue May 04 13:19:54 2010 +0100 @@ -110,11 +110,11 @@ CYGHWR_HAL_STM32_GPIO_SET( chan->txpin ); cr2 = CYGHWR_HAL_STM32_UART_CR2_STOP_1; - HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR2, cr2 ); + HAL_WRITE_UINT16( base+CYGHWR_HAL_STM32_UART_CR2, cr2 ); cr1 = CYGHWR_HAL_STM32_UART_CR1_M_8; cr1 |= CYGHWR_HAL_STM32_UART_CR1_TE | CYGHWR_HAL_STM32_UART_CR1_RE; - HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); + HAL_WRITE_UINT16( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); // Set up Baud rate chan->baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD; @@ -122,7 +122,7 @@ // Enable the uart cr1 |= CYGHWR_HAL_STM32_UART_CR1_UE; - HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); + HAL_WRITE_UINT16( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); } @@ -135,10 +135,10 @@ do { - HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_SR, sr ); + HAL_READ_UINT16( base + CYGHWR_HAL_STM32_UART_SR, sr ); } while ((sr & CYGHWR_HAL_STM32_UART_SR_TXE) == 0); - HAL_WRITE_UINT32( base + CYGHWR_HAL_STM32_UART_DR, c ); + HAL_WRITE_UINT16( base + CYGHWR_HAL_STM32_UART_DR, c ); CYGARC_HAL_RESTORE_GP(); } @@ -151,12 +151,12 @@ cyg_uint32 c; CYGARC_HAL_SAVE_GP(); - HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_SR, sr ); + HAL_READ_UINT16( base + CYGHWR_HAL_STM32_UART_SR, sr ); if( (sr & CYGHWR_HAL_STM32_UART_SR_RXNE) == 0 ) return false; - HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_DR, c ); + HAL_READ_UINT16( base + CYGHWR_HAL_STM32_UART_DR, c ); *ch = (cyg_uint8)c; @@ -246,17 +246,17 @@ chan->irq_state = 1; HAL_INTERRUPT_ACKNOWLEDGE( chan->isr_vector ); HAL_INTERRUPT_UNMASK( chan->isr_vector ); - HAL_READ_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); + HAL_READ_UINT16( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); cr1 |= CYGHWR_HAL_STM32_UART_CR1_RXNEIE; - HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); + HAL_WRITE_UINT16( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); break; case __COMMCTL_IRQ_DISABLE: ret = chan->irq_state; chan->irq_state = 0; HAL_INTERRUPT_MASK( chan->isr_vector ); - HAL_READ_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); + HAL_READ_UINT16( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); cr1 &= ~CYGHWR_HAL_STM32_UART_CR1_RXNEIE; - HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); + HAL_WRITE_UINT16( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); break; case __COMMCTL_DBG_ISR_VECTOR: ret = chan->isr_vector; --------------060901010905020303040904--