MPC8xx Quicc SMC Driver Lockup

MPC8xx Quicc SMC Driver Lockup

[Retallack, Mark]

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Hi, 

I have found an issue with the SMC (and SCC) quicc serial driver where if the CPM is under heavy load, the serial driver will stop transmitting any data which can lead to the serial driver locking up (if using buffered serial driver and blocking writes). This issue shows up when the Serial driver is re-configured.

This is caused by the CPM CP access code within the SMC/SCC serial driver not checking for the Busy flag (FLG) to be clear before continuing. This means that if the SMC is re-configured it may not be restarted. The attached patch performs a wait while the busy flag is active. 

I have also changed the sequence of the SMC UART set-up so the STOP TRANSMIT command is executed before the SMCMR[TEN] bit is cleared. Reading the MPC850 user manual suggests that this is the "more correct" way of performing a re-configuration of the SMC, it would be useful to get other peoples feedback on this change, I am not sure it will make a difference. 

Thanks in advance
Mark Retallack 

[-- Attachment #2: quiccWaitCP.patch --]
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diff -r -u5 -N -x CVS -x '*~' -x '.#*' clean/ecos/packages/devs/serial/powerpc/quicc/current/ChangeLog devo/ecos/packages/devs/serial/powerpc/quicc/current/ChangeLog
--- clean/ecos/packages/devs/serial/powerpc/quicc/current/ChangeLog	2009-01-29 17:48:42.000000000 +0000
+++ devo/ecos/packages/devs/serial/powerpc/quicc/current/ChangeLog	2010-12-06 12:07:16.000000000 +0000
@@ -1,5 +1,9 @@
+2010-12-06 Mark Retallack <mark.retallack@siemens.com>
+
+        * src/quicc_smc_serial.c: Wait for CPM Busy Flag to clear on write to CP Command Register
+
 2006-01-27 Will Wagner <willw@carallon.com>
 
         * src/quicc_smc_serial.h: Removed unused structure
         * src/quicc_smc_serial.c(quicc_smc_serial_config_port): Corrected CLEN in SMCMR
         * src/quicc_smc_serial.c(quicc_smc_serial_DSR & quicc_scc_serial_DSR): Better handling of frame and parity errors
diff -r -u5 -N -x CVS -x '*~' -x '.#*' clean/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c devo/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c
--- clean/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c	2009-01-29 17:48:42.000000000 +0000
+++ devo/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c	2010-12-06 11:48:37.000000000 +0000
@@ -337,27 +337,32 @@
     cyg_uint32 _lcr;
     EPPC *eppc = eppc_base();
     volatile struct smc_regs *ctl = (volatile struct smc_regs *)smc_chan->ctl;
 
     if (baud_divisor == 0) return false;
+    // Stop transmitter while changing baud rate
+    eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_StopTx;
+    while (eppc->cp_cr & QUICC_SMC_CMD_Go )
+        continue;
+    HAL_IO_BARRIER();  // Inforce I/O ordering
     // Disable channel during setup
     ctl->smc_smcmr = QUICC_SMCMR_UART;  // Disabled, UART mode
     HAL_IO_BARRIER();  // Inforce I/O ordering
     // Disable port interrupts while changing hardware
     _lcr = QUICC_SMCMR_CLEN(new_config->word_length + ((new_config->parity == CYGNUM_SERIAL_PARITY_NONE)? 0: 1) + ((new_config->stop == CYGNUM_SERIAL_STOP_2)? 2: 1)) |
         smc_select_stop_bits[new_config->stop] |
         smc_select_parity[new_config->parity];
-    // Stop transmitter while changing baud rate
-    eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_StopTx;
     HAL_IO_BARRIER();  // Inforce I/O ordering
     // Set baud rate generator
     *smc_chan->brg = 0x10000 | (UART_BITRATE(baud_divisor)<<1);
 
     // Enable channel with new configuration
     ctl->smc_smcmr = QUICC_SMCMR_UART|QUICC_SMCMR_TEN|QUICC_SMCMR_REN|_lcr;
     HAL_IO_BARRIER();  // Inforce I/O ordering
     eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_RestartTx;
+    while (eppc->cp_cr & QUICC_SMC_CMD_Go )
+        continue;
     if (new_config != &chan->config) {
         chan->config = *new_config;
     }
     return true;
 }
@@ -451,10 +456,12 @@
     /*
      *  Reset Rx & Tx params
      */
     HAL_IO_BARRIER();  // Inforce I/O ordering
     eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_InitTxRx;
+    while (eppc->cp_cr & QUICC_SMC_CMD_Go )
+        continue;
     HAL_IO_BARRIER();  // Inforce I/O ordering
     /*
      *  Clear any previous events. Enable interrupts.
      *  (Section 16.15.7.14 and 16.15.7.15)
      */
@@ -489,11 +496,12 @@
     /*
      *  Init Rx & Tx params for SCCX
      */
     HAL_IO_BARRIER();  // Inforce I/O ordering
     eppc->cp_cr = QUICC_CPM_CR_INIT_TXRX | scc_chan->channel | QUICC_CPM_CR_BUSY;
-
+    while (eppc->cp_cr & QUICC_CPM_CR_BUSY )
+        continue;
     HAL_IO_BARRIER();  // Inforce I/O ordering
     regs->scc_gsmr_l |= (QUICC_SCC_GSMR_L_Tx | QUICC_SCC_GSMR_L_Rx);  // Enable Rx, Tx
     if (new_config != &chan->config) {
         chan->config = *new_config;
     }
@@ -601,10 +609,12 @@
     /*
      *  Reset Rx & Tx params
      */
     HAL_IO_BARRIER();  // Inforce I/O ordering
     eppc->cp_cr = scc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_InitTxRx;
+    while (eppc->cp_cr & QUICC_SMC_CMD_Go )
+        continue;
     /*
      *  Clear any previous events. Enable interrupts.
      *  (Section 16.15.7.14 and 16.15.7.15)
      */
     HAL_IO_BARRIER();  // Inforce I/O ordering

Re: MPC8xx Quicc SMC Driver Lockup

[Sergei Gavrikov]

On Mon, 6 Dec 2010, Retallack, Mark wrote:

> Hi, 
> 
> I have found an issue with the SMC (and SCC) quicc serial driver where
> if the CPM is under heavy load, the serial driver will stop
> transmitting any data which can lead to the serial driver locking up
> (if using buffered serial driver and blocking writes). This issue
> shows up when the Serial driver is re-configured.
> 
> This is caused by the CPM CP access code within the SMC/SCC serial
> driver not checking for the Busy flag (FLG) to be clear before
> continuing. This means that if the SMC is re-configured it may not be
> restarted. The attached patch performs a wait while the busy flag is
> active. 
> 
> I have also changed the sequence of the SMC UART set-up so the STOP
> TRANSMIT command is executed before the SMCMR[TEN] bit is cleared.
> Reading the MPC850 user manual suggests that this is the "more
> correct" way of performing a re-configuration of the SMC, it would be
> useful to get other peoples feedback on this change, I am not sure it
> will make a difference. 

Hi Mark,

I looked on the patch and tested build process. The patch looks fine
*for me*, but, as I have not the same targets, I cannot test run-time
stuff. Could someone from maintainers, please, put his hands on this?
Or what could be your verdict?

Thank you,
Sergei

> Thanks in advance
> Mark Retallack 

Re: MPC8xx Quicc SMC Driver Lockup

[Sergei Gavrikov]

On Tue, 7 Dec 2010, Sergei Gavrikov wrote:
> On Mon, 6 Dec 2010, Retallack, Mark wrote:
> 
> > I have found an issue with the SMC (and SCC) quicc serial driver where
> > if the CPM is under heavy load, the serial driver will stop
> > transmitting any data which can lead to the serial driver locking up
> > (if using buffered serial driver and blocking writes). This issue
> > shows up when the Serial driver is re-configured.

[snip]

> I looked on the patch and tested build process. The patch looks fine
> *for me*, but, as I have not the same targets, I cannot test run-time
> stuff. Could someone from maintainers, please, put his hands on this?
> Or what could be your verdict?

I hope that silence gives consent. Checked-in. Mark, thank you for your
contribution.

Sergei