[Bug 1001815] New: Freescale DSPI avoid Rx DMA if transfer fits in FIFO.

[Bug 1001815] New: Freescale DSPI avoid Rx DMA if transfer fits in FIFO.

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            Bug ID: 1001815
           Summary: Freescale DSPI avoid Rx DMA if transfer fits in FIFO.
           Product: eCos
           Version: CVS
            Target: freescale_twr_k70f120m (Freescale Kinetis TWR-K70F120M
                    board)
  Architecture/Host Cortex-M
                OS:
            Status: NEW
          Severity: enhancement
          Priority: low
         Component: Patches and contributions
          Assignee: unassigned@bugs.ecos.sourceware.org
          Reporter: ilijak@siva.com.mk
                CC: ecos-patches@ecos.sourceware.org
        Depends on: 1001814

Created attachment 2157
  --> http://bugs.ecos.sourceware.org/attachment.cgi?id=2157&action=edit
DSPI Rx DMA avoid

Current DSPI avoids Tx DMA when transfer fits in DSPI FIFO (typically 4 bytes).
The submitted patch does the same also for Rx. The benefit should be
considerable especially in cached systems due to avoidance of cache
invalidation.

Additionally the patch implements DSPI clock gating enable as per bug 1001814.

Ilija

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[Bug 1001815] Freescale DSPI avoid Rx DMA if transfer fits in FIFO.

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Ilija Kocho <ilijak@siva.com.mk> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Attachment #2157|0                           |1
        is obsolete|                            |

--- Comment #1 from Ilija Kocho <ilijak@siva.com.mk> ---
Created attachment 2164
  --> http://bugs.ecos.sourceware.org/attachment.cgi?id=2164&action=edit
DSPI Rx DMA avoid compatible with attachment 2162

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[Bug 1001815] Freescale DSPI avoid Rx DMA if transfer fits in FIFO.

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--- Comment #2 from Ilija Kocho <ilijak@siva.com.mk> ---
Created attachment 2166
  --> http://bugs.ecos.sourceware.org/attachment.cgi?id=2166&action=edit
Bug fix to dspi_transaction_end 130407-0213 increment to Attachment 2164.

This patch fixes a race condition bug in dspi_transaction_end(). The bug was
exposed during Mike Jones testing of bug 1001814. I thank Mike for testing.

The patch is incremental to attachment 2167

Ilija

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[Bug 1001815] Freescale DSPI avoid Rx DMA if transfer fits in FIFO.

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--- Comment #3 from Ilija Kocho <ilijak@siva.com.mk> ---
Checked in. Thank to Mike Jones for testing.
Ilija

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[Bug 1001815] Freescale DSPI avoid Rx DMA if transfer fits in FIFO.

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http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001815

Bug 1001815 depends on bug 1001814, which changed state.

Bug 1001814 Summary: Kinetis clock gating
http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001814

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|---                         |CURRENTRELEASE

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[Bug 1001815] Freescale DSPI avoid Rx DMA if transfer fits in FIFO.

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http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001815

Ilija Kocho <ilijak@siva.com.mk> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|---                         |CURRENTRELEASE

--- Comment #4 from Ilija Kocho <ilijak@siva.com.mk> ---
Checked in a while ago.
Closing

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[Bug 1001815] Freescale DSPI avoid Rx DMA if transfer fits in FIFO.

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Ilija Kocho <ilijak@siva.com.mk> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|RESOLVED                    |REOPENED
         Resolution|CURRENTRELEASE              |---

--- Comment #5 from Ilija Kocho <ilijak@siva.com.mk> ---
There's a bug that in some circumstances causes erratic behaviour. This is due
to DMA not being disabled when it is not used.

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[Bug 1001815] Freescale DSPI avoid Rx DMA if transfer fits in FIFO.

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--- Comment #6 from Ilija Kocho <ilijak@siva.com.mk> ---
Created attachment 2237
  --> http://bugs.ecos.sourceware.org/attachment.cgi?id=2237&action=edit
Disable eDMA when not used incremental 130518

This patch disables eDMA when it is not used and enables when necessary.

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[Bug 1001815] Freescale DSPI avoid Rx DMA if transfer fits in FIFO.

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Ilija Kocho <ilijak@siva.com.mk> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Depends on|                            |1001838

--- Comment #7 from Ilija Kocho <ilijak@siva.com.mk> ---
In addition the CDL part attachment 2237 complements attachment 2226 of bug
1001838

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[Bug 1001815] Freescale DSPI avoid Rx DMA if transfer fits in FIFO.

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Ilija Kocho <ilijak@siva.com.mk> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Attachment #2166|0                           |1
        is obsolete|                            |

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[Bug 1001815] Freescale DSPI avoid Rx DMA if transfer fits in FIFO.

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Ilija Kocho <ilijak@siva.com.mk> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Attachment #2164|0                           |1
        is obsolete|                            |

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[Bug 1001815] Freescale DSPI avoid Rx DMA if transfer fits in FIFO.

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http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001815

Ilija Kocho <ilijak@siva.com.mk> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Attachment #2237|0                           |1
        is obsolete|                            |

--- Comment #8 from Ilija Kocho <ilijak@siva.com.mk> ---
Created attachment 2244
  --> http://bugs.ecos.sourceware.org/attachment.cgi?id=2244&action=edit
Disable eDMA when not used. 130602

The previous patch had problems with DMA, It should be fixed now.

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[Bug 1001815] Freescale DSPI avoid Rx DMA if transfer fits in FIFO.

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http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001815

Ilija Kocho <ilijak@siva.com.mk> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|REOPENED                    |RESOLVED
         Resolution|---                         |CURRENTRELEASE

--- Comment #9 from Ilija Kocho <ilijak@siva.com.mk> ---
Checked in.

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[Bug 1001815] Freescale DSPI avoid Rx DMA if transfer fits in FIFO.

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http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001815

Bug 1001815 depends on bug 1001838, which changed state.

Bug 1001838 Summary: Freescale EDMA CDL dependency calculation
http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001838

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |CURRENTRELEASE

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