From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 11407 invoked by alias); 3 May 2013 17:48:42 -0000 Mailing-List: contact ecos-patches-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: ecos-patches-owner@ecos.sourceware.org Received: (qmail 11383 invoked by uid 89); 3 May 2013 17:48:42 -0000 X-Spam-SWARE-Status: No, score=-2.8 required=5.0 tests=AWL,BAYES_00,KHOP_RCVD_UNTRUST,KHOP_THREADED,RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.1 Received: from hagrid.ecoscentric.com (HELO mail.ecoscentric.com) (212.13.207.197) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Fri, 03 May 2013 17:48:41 +0000 Received: from localhost (hagrid.ecoscentric.com [127.0.0.1]) by mail.ecoscentric.com (Postfix) with ESMTP id 659F34680012 for ; Fri, 3 May 2013 18:48:39 +0100 (BST) Received: from mail.ecoscentric.com ([127.0.0.1]) by localhost (hagrid.ecoscentric.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id TXF0z+ZDz2Ep; Fri, 3 May 2013 18:48:36 +0100 (BST) From: bugzilla-daemon@bugs.ecos.sourceware.org To: ecos-patches@ecos.sourceware.org Subject: [Bug 1001837] Rich FlexBus RAM layout Date: Fri, 03 May 2013 17:48:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: eCos X-Bugzilla-Component: Patches and contributions X-Bugzilla-Keywords: X-Bugzilla-Severity: enhancement X-Bugzilla-Who: ilijak@siva.com.mk X-Bugzilla-Status: NEW X-Bugzilla-Priority: low X-Bugzilla-Assigned-To: unassigned@bugs.ecos.sourceware.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Bugzilla-URL: http://bugs.ecos.sourceware.org/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-SW-Source: 2013-05/txt/msg00011.txt.bz2 Please do not reply to this email, use the link below. http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001837 --- Comment #12 from Ilija Kocho --- (In reply to comment #7) > I assume from Ilija's comments that DMA bypasses the cache, hence the need > to invalidate it. > [snip] > I assume the TCD limitation is because the eDMA logic in the device is > connected tightly with the memory bus logic and can't route through the > cache, similar to how DMA works directly on memory without the cache. eDMA has no access to cache, but the problem could be (also) solved with cache synchronisation/invalidation. However, it would require extra CPU time and since TCD typically occupy little memory (even cumulative), for best performance I have chosen to put them in SRAM [by default]. Same discussion applies to Ethernet buffer descriptors. [snip] -- You are receiving this mail because: You are on the CC list for the bug.