Re: [PATCH] when building using binutils 2.20:

[Nick Garnett <nickg@ecoscentric.com>]

Spencer Oliver <spen@spen-soft.co.uk> writes:

> cortex_m3: buildfix for binutils 2.20
> 
> when building using binutils 2.20:
>   - swi inst now requires an argument.
>   - msr psp,sp is not allowed.

I've written a ChangeLog entry for you. The following patch has been
applied:

Index: ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/cortexm/arch/current/ChangeLog,v
retrieving revision 1.10
diff -u -5 -r1.10 ChangeLog
--- ChangeLog	4 Mar 2009 16:29:55 -0000	1.10
+++ ChangeLog	17 May 2010 11:36:08 -0000
@@ -1,5 +1,14 @@
+2010-05-17  Spencer Oliver <spen@spen-soft.co.uk>
+
+	* include/hal_intr.h (HAL_INTERRUPT_STACK_CALL_PENDING_DSRS):
+	* src/hal_misc.c (hal_reset_vsr): Add 0 argument to SWI.
+
+	* src/vectors.S (hal_switch_state_vsr): Eliminate "msr psp,sp",
+	which is now deprecated.
+	(hal_pendable_svc_vsr): Add 0 argument to SWI.
+
 2009-02-27  Simon Kallweit  <simon.kallweit@intefo.ch>
 
 	* include/hal_io.h: Added system control register definitions 
 
 2009-02-13  Nick Garnett  <nickg@ecoscentric.com>
Index: include/hal_intr.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/cortexm/arch/current/include/hal_intr.h,v
retrieving revision 1.4
diff -u -5 -r1.4 hal_intr.h
--- include/hal_intr.h	29 Jan 2009 17:49:15 -0000	1.4
+++ include/hal_intr.h	17 May 2010 11:36:09 -0000
@@ -296,11 +296,11 @@
 __externC void hal_call_dsrs_vsr(void);
 #define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS()         \
 {                                                       \
     __asm__ volatile (                                  \
         "ldr     r3,=hal_call_dsrs_vsr          \n"     \
-        "swi                                    \n"     \
+        "swi 0                                  \n"     \
         :                                               \
         :                                               \
         : "r3"                                          \
         );                                              \
 }
Index: src/hal_misc.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/cortexm/arch/current/src/hal_misc.c,v
retrieving revision 1.5
diff -u -5 -r1.5 hal_misc.c
--- src/hal_misc.c	9 Feb 2009 15:57:49 -0000	1.5
+++ src/hal_misc.c	17 May 2010 11:36:09 -0000
@@ -183,11 +183,11 @@
     // We don't need to do this for RAM startup since the ROM code
     // will have already done it.
 
     hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_switch_state_vsr;    
 
-    __asm__ volatile( "swi" );
+    __asm__ volatile( "swi 0" );
 
     hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_default_svc_vsr;
     
 #endif // !defined(CYG_HAL_STARTUP_RAM)
     
Index: src/vectors.S
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/cortexm/arch/current/src/vectors.S,v
retrieving revision 1.2
diff -u -5 -r1.2 vectors.S
--- src/vectors.S	29 Jan 2009 17:49:15 -0000	1.2
+++ src/vectors.S	17 May 2010 11:36:09 -0000
@@ -128,11 +128,12 @@
         
         mov     r0,#2                   // Set CONTROL register to 2
         msr     control,r0
         isb                             // Insert a barrier
         
-        msr     psp,sp                  // Copy SP to PSP
+        mov     r0,sp
+        msr     psp,r0                  // Copy SP to PSP
 
 #if !defined(CYGPKG_KERNEL)
         sub     sp,#(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE/2)
 #endif        
         
@@ -272,11 +273,11 @@
         .thumb_func
         .type   hal_interrupt_end_done, %function
 hal_interrupt_end_done:
 
         ldr     r3,=hal_interrupt_end_vsr
-        swi
+        swi 0
         
 //==========================================================================        
 // Interrupt end VSR
 //
 // This is the SVC VSR invoked by hal_interrupt_end_done to restore the



-- 
Nick Garnett                                      eCos Kernel Architect
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