* STM32 SPI bus 3 pin contention patch.
@ 2009-02-10 11:09 Chris Holgate
2009-02-10 16:28 ` Nick Garnett
0 siblings, 1 reply; 2+ messages in thread
From: Chris Holgate @ 2009-02-10 11:09 UTC (permalink / raw)
To: ecos-patches
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The attached patch adds some additional comments to CDL file regarding
the JTAG/SPI3 pin contention discussed here:
http://ecos.sourceware.org/ml/ecos-discuss/2009-02/msg00050.html
It also provides a new CDL option to automatically disable the JTAG port
when SPI bus 3 is initialised. Tested using the simple SPI loopback test.
Chris.
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diff -r -u5 cvs-06.02.09/ecos/packages//devs/spi/cortexm/stm32/current/cdl/spi_stm32.cdl working-10.02.08/ecos/packages//devs/spi/cortexm/stm32/current/cdl/spi_stm32.cdl
--- cvs-06.02.09/ecos/packages//devs/spi/cortexm/stm32/current/cdl/spi_stm32.cdl 2009-02-04 11:42:35.000000000 +0000
+++ working-10.02.08/ecos/packages//devs/spi/cortexm/stm32/current/cdl/spi_stm32.cdl 2009-02-10 10:28:52.000000000 +0000
@@ -163,15 +163,28 @@
}
cdl_component CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3 {
display "ST STM32 SPI bus 3"
description "
- Enable SPI bus 3 on the STM32 device.
+ Enable SPI bus 3 on the STM32 device. Note that SPI bus 3 shares pins
+ with the JTAG port which means that debug should ideally be disabled
+ on startup. However, there is also the option of disabling it during
+ SPI bus initialisation instead.
"
flavor bool
default_value false
+ cdl_option CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3_DISABLE_DEBUG_PORT {
+ display "Disable debug port"
+ description "
+ When set the debug port will automatically be disabled on
+ initialising SPI bus 3, freeing up the SPI interface pins.
+ "
+ flavor bool
+ default_value false
+ }
+
cdl_option CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3_CS_GPIOS {
display "SPI chip selects"
description "
This is a comma separated list of GPIOs which are to be used as chip
select lines for the SPI bus. For the purposes of specifying
diff -r -u5 cvs-06.02.09/ecos/packages//devs/spi/cortexm/stm32/current/ChangeLog working-10.02.08/ecos/packages//devs/spi/cortexm/stm32/current/ChangeLog
--- cvs-06.02.09/ecos/packages//devs/spi/cortexm/stm32/current/ChangeLog 2009-02-10 09:42:26.000000000 +0000
+++ working-10.02.08/ecos/packages//devs/spi/cortexm/stm32/current/ChangeLog 2009-02-10 10:50:44.000000000 +0000
@@ -1,5 +1,11 @@
+2009-02-10 Chris Holgate <chris@zynaptic.com>
+
+ * src/spi_stm32.c:
+ * cdl/spi_stm32.cdl:
+ Add option to automatically disable JTAG port when initialising SPI3.
+
2009-02-10 Nick Garnett <nickg@ecoscentric.com>
* src/spi_stm32.c (bus3_setup): Fix typo.
2009-02-05 Nick Garnett <nickg@ecoscentric.com>
diff -r -u5 cvs-06.02.09/ecos/packages//devs/spi/cortexm/stm32/current/src/spi_stm32.c working-10.02.08/ecos/packages//devs/spi/cortexm/stm32/current/src/spi_stm32.c
--- cvs-06.02.09/ecos/packages//devs/spi/cortexm/stm32/current/src/spi_stm32.c 2009-02-10 09:42:26.000000000 +0000
+++ working-10.02.08/ecos/packages//devs/spi/cortexm/stm32/current/src/spi_stm32.c 2009-02-10 10:04:08.000000000 +0000
@@ -612,10 +612,20 @@
// Initialise SPI interfaces on startup.
void cyg_spi_cortexm_stm32_init
(void)
{
+#if defined(CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3) && \
+ defined(CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3_DISABLE_DEBUG_PORT)
+ // Disable debug port, freeing up SPI bus 3 pins.
+ cyg_uint32 reg_val;
+ HAL_READ_UINT32 (CYGHWR_HAL_STM32_AFIO + CYGHWR_HAL_STM32_AFIO_MAPR, reg_val);
+ reg_val &= ~((cyg_uint32) CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_MASK);
+ reg_val |= CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_SWDPDIS;
+ HAL_WRITE_UINT32 (CYGHWR_HAL_STM32_AFIO + CYGHWR_HAL_STM32_AFIO_MAPR, reg_val);
+#endif
+
#ifdef CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1
stm32_spi_bus_setup (&cyg_spi_stm32_bus1);
#endif
#ifdef CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS2
diff -r -u5 cvs-06.02.09/ecos/packages//hal/cortexm/stm32/var/current/ChangeLog working-10.02.08/ecos/packages//hal/cortexm/stm32/var/current/ChangeLog
--- cvs-06.02.09/ecos/packages//hal/cortexm/stm32/var/current/ChangeLog 2009-02-10 09:42:36.000000000 +0000
+++ working-10.02.08/ecos/packages//hal/cortexm/stm32/var/current/ChangeLog 2009-02-10 10:52:10.000000000 +0000
@@ -1,5 +1,9 @@
+2009-02-10 Chris Holgate <chris@zynaptic.com>
+
+ * include/var_io.h: Add mask for CYGHWR_HAL_STM32_AFIO_MAPR_SWJ.
+
2009-02-04 Nick Garnett <nickg@ecoscentric.com>
* include/var_intr.h: Various fixes to allow external interrupts
to work.
diff -r -u5 cvs-06.02.09/ecos/packages//hal/cortexm/stm32/var/current/include/var_io.h working-10.02.08/ecos/packages//hal/cortexm/stm32/var/current/include/var_io.h
--- cvs-06.02.09/ecos/packages//hal/cortexm/stm32/var/current/include/var_io.h 2009-02-10 09:42:36.000000000 +0000
+++ working-10.02.08/ecos/packages//hal/cortexm/stm32/var/current/include/var_io.h 2009-02-10 10:02:41.000000000 +0000
@@ -428,10 +428,11 @@
#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_FULL VALUE_(24,0)
#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_NORST VALUE_(24,1)
#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_SWDPEN VALUE_(24,2)
#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_SWDPDIS VALUE_(24,4)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_MASK VALUE_(24,7)
// The following macros are used to generate the bitfields for setting up
// external interrupts. For example, CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTC(12)
// will generate the bitfield which when ORed into the EXTICR4 register will
// set up C12 as the external interrupt pin for the EXTI12 interrupt.
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: STM32 SPI bus 3 pin contention patch.
2009-02-10 11:09 STM32 SPI bus 3 pin contention patch Chris Holgate
@ 2009-02-10 16:28 ` Nick Garnett
0 siblings, 0 replies; 2+ messages in thread
From: Nick Garnett @ 2009-02-10 16:28 UTC (permalink / raw)
To: Chris Holgate; +Cc: ecos-patches
Chris Holgate <chris@zynaptic.com> writes:
> The attached patch adds some additional comments to CDL file regarding
> the JTAG/SPI3 pin contention discussed here:
>
> http://ecos.sourceware.org/ml/ecos-discuss/2009-02/msg00050.html
>
> It also provides a new CDL option to automatically disable the JTAG port
> when SPI bus 3 is initialised. Tested using the simple SPI loopback test.
Thanks, checked in.
--
Nick Garnett eCos Kernel Architect
eCosCentric Limited http://www.eCosCentric.com The eCos experts
Barnwell House, Barnwell Drive, Cambridge, UK. Tel: +44 1223 245571
Registered in England and Wales: Reg No: 4422071
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2009-02-10 16:28 ` Nick Garnett
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