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* [PATCH] RISC-V: Improve riscv64 core file support.
@ 2018-12-27 23:25 Jim Wilson
  2019-01-08 22:58 ` Mark Wielaard
  0 siblings, 1 reply; 2+ messages in thread
From: Jim Wilson @ 2018-12-27 23:25 UTC (permalink / raw)
  To: elfutils-devel; +Cc: Jim Wilson

This fixes two problems.  The offset for x1 is changed from 1 to 8 because this
is a byte offset not a register skip count.  Support for reading the PC value
is added.  This requires changing the testsuite to match the new readelf
output for coredumps.

Signed-off-by: Jim Wilson <jimw@sifive.com>
---
 backends/ChangeLog                  |  5 +++++
 backends/riscv_corenote.c           |  9 +++++++-
 tests/ChangeLog                     |  4 ++++
 tests/run-readelf-mixed-corenote.sh | 34 ++++++++++++++---------------
 4 files changed, 34 insertions(+), 18 deletions(-)

diff --git a/backends/ChangeLog b/backends/ChangeLog
index e2a02812..c8234072 100644
--- a/backends/ChangeLog
+++ b/backends/ChangeLog
@@ -1,3 +1,8 @@
+2018-12-27  Jim Wilson  <jimw@sifive.com>
+
+	* riscv_corenote.c (prstatus_regs): Change offset from 1 to 8.
+	(PRSTATUS_REGSET_ITEMS): New.
+
 2018-11-06  Mark Wielaard  <mark@klomp.org>
 
 	* x86_64_symbol.c (x86_64_section_type_name): New function.
diff --git a/backends/riscv_corenote.c b/backends/riscv_corenote.c
index 37cce7e3..afb84bee 100644
--- a/backends/riscv_corenote.c
+++ b/backends/riscv_corenote.c
@@ -53,8 +53,15 @@
 
 static const Ebl_Register_Location prstatus_regs[] =
   {
-    { .offset = 1, .regno = 1, .count = 31, .bits = 64 } /* x1..x31 */
+    { .offset = 8, .regno = 1, .count = 31, .bits = 64 } /* x1..x31 */
   };
 #define PRSTATUS_REGS_SIZE	(32 * 8)
 
+#define PRSTATUS_REGSET_ITEMS						\
+  {									\
+    .name = "pc", .type = ELF_T_ADDR, .format = 'x',			\
+    .offset = offsetof (struct EBLHOOK(prstatus), pr_reg[0]),		\
+    .group = "register", .pc_register = true				\
+  }
+
 #include "linux-core-note.c"
diff --git a/tests/ChangeLog b/tests/ChangeLog
index 1382e40a..71b24e09 100644
--- a/tests/ChangeLog
+++ b/tests/ChangeLog
@@ -1,3 +1,7 @@
+2018-12-27  Jim Wilson  <jimw@sifive.com>
+
+	* run-readelf-mixed-corenote.sh: Update with new riscv64 output.
+
 2018-12-02  Mark Wielaard  <mark@klomp.org>
 
 	* testfile_gnu_props.32le.o.bz2: New testfile.
diff --git a/tests/run-readelf-mixed-corenote.sh b/tests/run-readelf-mixed-corenote.sh
index 07cfc39c..c960f1d6 100755
--- a/tests/run-readelf-mixed-corenote.sh
+++ b/tests/run-readelf-mixed-corenote.sh
@@ -660,23 +660,23 @@ Note segment of 1408 bytes at offset 0x388:
     sighold: <>
     pid: 6801, ppid: 1155, pgrp: 6801, sid: 1155
     utime: 0.000000, stime: 0.110000, cutime: 0.000000, cstime: 0.000000
-    fpvalid: 0
-    ra:    0x9a00000000000104  sp:    0x400000002000051c
-    gp:    0x280000003fff9812  tp:    0xd000000000000128
-    t0:   5764607523571106577  t1:   -432345563690696255
-    t2:  -5764607522497362661  s0:   5764607523034235171
-    s1:  -6629298650415654894  a0:     72057594037928196
-    a1:  -6341068275337658368  a2:  -5188146769657096173
-    a3:            1073715219  a4:   8646911284551352320
-    a5:   8646911285625067538  a6:   1729382256911463510
-    a7:             536876397  s2:  -1152921504606846976
-    s3:   1152921505322686797  s4:             536871337
-    s5:  -3458764513820540928  s6:  -9223372036138925403
-    s7:             715843991  s8:  -2594073385365405696
-    s9:   4611686019143218592  s10:            715850259
-    s11:            715850393  t3:   -432345564227567616
-    t4:    144115188075856379  t5:    216172782113783808
-    t6:   1152921504606846976
+    pc: 0x000000000001049a, fpvalid: 0
+    ra:    0x0000002000051c9a  sp:    0x0000003fff981240
+    gp:    0x0000000000012828  tp:    0x00000020000311d0
+    t0:          137439068496  t1:          137439288314
+    t2:                 74672  s0:          274871095888
+    s1:                 66724  a0:                     1
+    a1:          274871096232  a2:          274871096248
+    a3:                     0  a4:          274871095928
+    a5:             305419896  a6:          137440357656
+    a7:                     0  s2:          183254994416
+    s3:          137439062288  s4:                     0
+    s5:          183257703888  s6:          183256061824
+    s7:                     0  s8:          183252656348
+    s9:          183257666368  s10:         183257700608
+    s11:                    0  t3:                130042
+    t4:                     2  t5:                     3
+    t6:                 15632
   CORE                 136  PRPSINFO
     state: 0, sname: R, zomb: 0, nice: 0, flag: 0x0000000000400600
     uid: 0, gid: 0, pid: 6801, ppid: 1155, pgrp: 6801, sid: 1155
-- 
2.19.2

^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH] RISC-V: Improve riscv64 core file support.
  2018-12-27 23:25 [PATCH] RISC-V: Improve riscv64 core file support Jim Wilson
@ 2019-01-08 22:58 ` Mark Wielaard
  0 siblings, 0 replies; 2+ messages in thread
From: Mark Wielaard @ 2019-01-08 22:58 UTC (permalink / raw)
  To: Jim Wilson; +Cc: elfutils-devel

On Thu, Dec 27, 2018 at 03:25:49PM -0800, Jim Wilson wrote:
> This fixes two problems.  The offset for x1 is changed from 1 to 8 because this
> is a byte offset not a register skip count.  Support for reading the PC value
> is added.  This requires changing the testsuite to match the new readelf
> output for coredumps.

This commit looks perfect (but please keep the lines a bit smaller, so
git show looks ok on a 80 char term - yeah, I know how old school).
Pushed to master.

Thanks,

Mark

^ permalink raw reply	[flat|nested] 2+ messages in thread

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2019-01-08 22:58 ` Mark Wielaard

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