From: Ulrich Drepper <drepper@redhat.com>
To: Jim Wilson <jimw@sifive.com>, elfutils-devel@sourceware.org
Subject: Re: RISC-V disassembler
Date: Tue, 10 Sep 2019 04:27:00 -0000 [thread overview]
Message-ID: <81918d46-ee99-9850-2543-a59df045899a@redhat.com> (raw)
In-Reply-To: <fbc05d3d-6797-e0f9-91ca-9e75f733cda1@sifive.com>
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On 9/9/19 11:25 PM, Jim Wilson wrote:
> There is a testfile45.expect.bz2 that doesn't look like it is supposed
> to be part of the patch set. You probably don't want to commit that one.
Yes, I do. The x86-64 disassembler had a tiny whitespace bug exposed
through the code.
> There is a testcase for riscv64 but not for riscv32, though the code
> does look like it correctly handles rv32 versus rv64 decodes. A
> testcase for rv32 would be a nice improvement.
Well, if someone has the time.
> Otherwise, it looks pretty good at a first glance, and I'm not planning
> to do a full review. Seems to handle the obvious tricky cases
> correctly. It doesn't support rv128
This necessitates the introduction of ELFCLASS128 first.
> or the q (quadfloat) extension,
Yes, it does.
> We have binutils patches for the draft V
> (vector) and B (bit manipulation) extensions in branches in the
> github.com riscv repos, but these are still changing instruction
> mnemonics and encodings, so not ready for official trees yet.
Which is why I didn't add any of that.
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prev parent reply other threads:[~2019-09-10 4:27 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-07 9:18 Ulrich Drepper
2019-09-07 20:17 ` Mark Wielaard
2019-09-09 21:25 ` Jim Wilson
2019-09-10 4:27 ` Ulrich Drepper [this message]
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