[SCM] master: Convert more "register" to Register.REGISTER.

[cagney@sourceware.org]

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       via  133f583505e712fc4911f624e42262833a37e468 (commit)
      from  cb32a788e5ece3e8775f3def07d86e13ee14a64f (commit)

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- Log -----------------------------------------------------------------
commit 133f583505e712fc4911f624e42262833a37e468
Author: Andrew Cagney <cagney@toil.yyz.redhat.com>
Date:   Thu Nov 22 12:51:30 2007 -0500

    Convert more "register" to Register.REGISTER.
    
    frysk-core/frysk/proc/ChangeLog
    2007-11-22  Andrew Cagney  <cagney@redhat.com>
    
    	* X86BankRegisters.java (IA32_ON_X8664): Use
    	IndirectBankRegisterMap .add(Register) and
    	.add(Register,Register).

-----------------------------------------------------------------------

Summary of changes:
 frysk-core/frysk/proc/ChangeLog             |    4 ++
 frysk-core/frysk/proc/X86BankRegisters.java |   70 +++++++++++++-------------
 2 files changed, 39 insertions(+), 35 deletions(-)

First 500 lines of diff:
diff --git a/frysk-core/frysk/proc/ChangeLog b/frysk-core/frysk/proc/ChangeLog
index d64c8f1..f451009 100644
--- a/frysk-core/frysk/proc/ChangeLog
+++ b/frysk-core/frysk/proc/ChangeLog
@@ -1,5 +1,9 @@
 2007-11-22  Andrew Cagney  <cagney@redhat.com>
 
+	* X86BankRegisters.java (IA32_ON_X8664): Use
+	IndirectBankRegisterMap .add(Register) and
+	.add(Register,Register).
+
 	* IndirectBankRegisterMap.java (add(Register)): New.
 	(add(Register,Register)): New.
 
diff --git a/frysk-core/frysk/proc/X86BankRegisters.java b/frysk-core/frysk/proc/X86BankRegisters.java
index 9b6d6e0..b28c1e7 100644
--- a/frysk-core/frysk/proc/X86BankRegisters.java
+++ b/frysk-core/frysk/proc/X86BankRegisters.java
@@ -173,23 +173,23 @@ public class X86BankRegisters {
 
     public static BankRegisterMap IA32_ON_X8664
 	= new IndirectBankRegisterMap(ByteOrder.LITTLE_ENDIAN, IA32, X8664)
-	.add("eax", "rax")
-	.add("ebx", "rbx")
-	.add("ecx", "rcx")
-	.add("edx", "rdx")
-	.add("esi", "rsi")
-	.add("edi", "rdi")
-	.add("ebp", "rbp")
+	.add(IA32Registers.EAX, X8664Registers.RAX)
+	.add(IA32Registers.EBX, X8664Registers.RBX)
+	.add(IA32Registers.ECX, X8664Registers.RCX)
+	.add(IA32Registers.EDX, X8664Registers.RDX)
+	.add(IA32Registers.ESI, X8664Registers.RSI)
+	.add(IA32Registers.EDI, X8664Registers.RDI)
+	.add(IA32Registers.EBP, X8664Registers.RBP)
 	.add("cs", "cs")
 	.add("ds", "ds")
 	.add("es", "es")
 	.add("fs", "fs")
 	.add("gs", "gs")
 	.add("ss", "gs")
-	.add("orig_eax", "orig_rax")
-	.add("eip", "rip")
-	.add("eflags","rflags")
-	.add("esp", "rsp")
+	.add(IA32Registers.ORIG_EAX, X8664Registers.ORIG_RAX)
+	.add(IA32Registers.EIP, X8664Registers.RIP)
+	.add(IA32Registers.EFLAGS,X8664Registers.RFLAGS)
+	.add(IA32Registers.ESP, X8664Registers.RSP)
 	.add("cwd", "cwd")
 	.add("swd", "swd")
 	.add("twd", "ftw")
@@ -197,29 +197,29 @@ public class X86BankRegisters {
 	.add("fcs", 0)
 	.add("foo", "rdp")
 	.add("fos", 0)
-	.add("st0")
-	.add("st1")
-	.add("st2")
-	.add("st3")
-	.add("st4")
-	.add("st5")
-	.add("st6")
-	.add("st7")
-	.add("xmm0")
-	.add("xmm1")
-	.add("xmm2")
-	.add("xmm3")
-	.add("xmm4")
-	.add("xmm5")
-	.add("xmm6")
-	.add("xmm7")
-	.add("d0", "dr0")
-	.add("d1", "dr1")
-	.add("d2", "dr2")
-	.add("d3", "dr3")
-	.add("d4", "dr4")
-	.add("d5", "dr5")
-	.add("d6", "dr6")
-	.add("d7", "dr7")
+	.add(X87Registers.ST0)
+	.add(X87Registers.ST1)
+	.add(X87Registers.ST2)
+	.add(X87Registers.ST3)
+	.add(X87Registers.ST4)
+	.add(X87Registers.ST5)
+	.add(X87Registers.ST6)
+	.add(X87Registers.ST7)
+	.add(IA32Registers.XMM0)
+	.add(IA32Registers.XMM1)
+	.add(IA32Registers.XMM2)
+	.add(IA32Registers.XMM3)
+	.add(IA32Registers.XMM4)
+	.add(IA32Registers.XMM5)
+	.add(IA32Registers.XMM6)
+	.add(IA32Registers.XMM7)
+	.add(IA32Registers.D0, X8664Registers.DR0)
+	.add(IA32Registers.D1, X8664Registers.DR1)
+	.add(IA32Registers.D2, X8664Registers.DR2)
+	.add(IA32Registers.D3, X8664Registers.DR3)
+	.add(IA32Registers.D4, X8664Registers.DR4)
+	.add(IA32Registers.D5, X8664Registers.DR5)
+	.add(IA32Registers.D6, X8664Registers.DR6)
+	.add(IA32Registers.D7, X8664Registers.DR7)
 	;
 }


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