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From: jflavio@sourceware.org
To: frysk-cvs@sourceware.org
Subject: [SCM] master: Merge branch 'master' of ssh://sources.redhat.com/git/frysk
Date: Wed, 28 Nov 2007 21:40:00 -0000 [thread overview]
Message-ID: <20071128214039.4506.qmail@sourceware.org> (raw)
The branch, master has been updated
via 1e71dcb17fdefb823eeef9a67f0e27f616e86882 (commit)
via 38af65fc3da29c49822aeb2ef885f6ceb80aa2ae (commit)
from 83b71d8dbfed32527d4bace5f13fb7827fcff409 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email.
- Log -----------------------------------------------------------------
commit 1e71dcb17fdefb823eeef9a67f0e27f616e86882
Merge: 38af65fc3da29c49822aeb2ef885f6ceb80aa2ae 83b71d8dbfed32527d4bace5f13fb7827fcff409
Author: Jose Flavio Aguilar Paulino <joseflavio@gmail.com>
Date: Wed Nov 28 19:40:22 2007 -0200
Merge branch 'master' of ssh://sources.redhat.com/git/frysk
commit 38af65fc3da29c49822aeb2ef885f6ceb80aa2ae
Author: Jose Flavio Aguilar Paulino <joseflavio@gmail.com>
Date: Wed Nov 28 19:39:40 2007 -0200
Adding test values Registers and added Power32/64 to factory.
-----------------------------------------------------------------------
Summary of changes:
frysk-core/frysk/isa/ChangeLog | 4 +
frysk-core/frysk/isa/RegistersFactory.java | 2 +
.../proc/live/PtraceRegisterBanksFactory.java | 3 +-
frysk-core/frysk/testbed/ChangeLog | 4 +
frysk-core/frysk/testbed/RegsCase.java | 84 +++++++++++++++++++-
5 files changed, 94 insertions(+), 3 deletions(-)
First 500 lines of diff:
diff --git a/frysk-core/frysk/isa/ChangeLog b/frysk-core/frysk/isa/ChangeLog
index f467b7c..09245ef 100644
--- a/frysk-core/frysk/isa/ChangeLog
+++ b/frysk-core/frysk/isa/ChangeLog
@@ -1,3 +1,7 @@
+2007-11-28 Jose Flavio Aguilar Paulino <joseflavio@gmail.com>
+
+ * RegistersFactory.java: Adding Power32/64 registers to factory.
+
2007-11-26 Andrew Cagney <cagney@redhat.com>
* X8664Registers.java (XMM0, ..., XMM15): Delete.
diff --git a/frysk-core/frysk/isa/RegistersFactory.java b/frysk-core/frysk/isa/RegistersFactory.java
index 4ced9a8..31cf74f 100644
--- a/frysk-core/frysk/isa/RegistersFactory.java
+++ b/frysk-core/frysk/isa/RegistersFactory.java
@@ -48,6 +48,8 @@ public class RegistersFactory {
= new ISAMap("RegistersFactory")
.put(ISA.IA32, new IA32Registers())
.put(ISA.X8664, new X8664Registers())
+ .put(ISA.PPC32BE, new PPC32Registers())
+ .put(ISA.PPC64BE, new PPC64Registers())
;
static public Registers getRegisters(ISA isa) {
return (Registers)isaToRegisters.get(isa);
diff --git a/frysk-core/frysk/proc/live/PtraceRegisterBanksFactory.java b/frysk-core/frysk/proc/live/PtraceRegisterBanksFactory.java
index 74232f0..75aeed9 100644
--- a/frysk-core/frysk/proc/live/PtraceRegisterBanksFactory.java
+++ b/frysk-core/frysk/proc/live/PtraceRegisterBanksFactory.java
@@ -84,14 +84,13 @@ class PtraceRegisterBanksFactory {
private static ByteBuffer[] ppcBanksBE(int pid) {
ByteBuffer[] bankBuffers = new ByteBuffer[] {
- new RegisterSetByteBuffer(pid, RegisterSet.REGS),
new AddressSpaceByteBuffer(pid, AddressSpace.USR)
};
for (int i = 0; i < bankBuffers.length; i++) {
bankBuffers[i].order(ByteOrder.BIG_ENDIAN);
}
-
+ System.out.println("Usr Addr Space Size: " + bankBuffers[0].capacity());
return bankBuffers;
}
diff --git a/frysk-core/frysk/testbed/ChangeLog b/frysk-core/frysk/testbed/ChangeLog
index 01c6bb7..56ba41e 100644
--- a/frysk-core/frysk/testbed/ChangeLog
+++ b/frysk-core/frysk/testbed/ChangeLog
@@ -1,3 +1,7 @@
+2007-11-28 Jose Flavio Aguilar Paulino <joseflavio@gmail.com>
+
+ * RegsCase.java: Add the PowerPC32 general purpose register values.
+
2007-11-12 Andrew Cagney <cagney@redhat.com>
* DaemonBlockedAtSignal.java (DaemonBlockedAtSignal(File)): New.
diff --git a/frysk-core/frysk/testbed/RegsCase.java b/frysk-core/frysk/testbed/RegsCase.java
index 2078cff..6521e2b 100644
--- a/frysk-core/frysk/testbed/RegsCase.java
+++ b/frysk-core/frysk/testbed/RegsCase.java
@@ -43,6 +43,8 @@ import java.util.Map.Entry;
import frysk.isa.Register;
import frysk.isa.IA32Registers;
import frysk.isa.X8664Registers;
+import frysk.isa.PPC32Registers;
+import frysk.isa.PPC64Registers;
import frysk.isa.ISA;
import frysk.isa.ISAMap;
import frysk.proc.Task;
@@ -347,7 +349,87 @@ public abstract class RegsCase extends TestLib {
.put(X8664Registers.RIP, "crash")
;
+ private Values PPC32 = new Values()
+ .put(PPC32Registers.GPR0,
+ new byte[] { (byte)0xa3,(byte)0x9c,0x20,(byte)0x08 })
+ .put(PPC32Registers.GPR1,
+ new byte[] { (byte)0x3a,(byte)0x82,0x27,(byte)0xf1 })
+ .put(PPC32Registers.GPR2,
+ new byte[] { (byte)0x1b,(byte)0x12,(byte)0xa0,(byte)0xa2 })
+ .put(PPC32Registers.GPR3,
+ new byte[] { (byte)0xe2,(byte)0xab,(byte)0xff,(byte)0xcc })
+ .put(PPC32Registers.GPR4,
+ new byte[] { (byte)0xc4,(byte)0x46,(byte)0xeb,(byte)0xf1 })
+ .put(PPC32Registers.GPR5,
+ new byte[] { (byte)0xa9,(byte)0x94,0x2a,(byte)0x4e })
+ .put(PPC32Registers.GPR6,
+ new byte[] { (byte)0x55,(byte)0xa2,(byte)0x92,(byte)0x51 })
+ .put(PPC32Registers.GPR7,
+ new byte[] { (byte)0x4f,(byte)0x61,0x6e,(byte)0xf2 })
+ .put(PPC32Registers.GPR8,
+ new byte[] { (byte)0xf1,(byte)0x76,(byte)0xef,(byte)0x4d })
+ .put(PPC32Registers.GPR9,
+ new byte[] { (byte)0xdf,(byte)0xac,0x22,(byte)0x56 })
+ .put(PPC32Registers.GPR10,
+ new byte[] { (byte)0xad,(byte)0x1a,(byte)0x8a,(byte)0x99 })
+ .put(PPC32Registers.GPR11,
+ new byte[] { (byte)0x11,(byte)0x2e,(byte)0x88,(byte)0xab })
+ .put(PPC32Registers.GPR12,
+ new byte[] { (byte)0xf7,(byte)0xfc,(byte)0xd1,(byte)0xf2 })
+ .put(PPC32Registers.GPR13,
+ new byte[] { (byte)0x88,(byte)0x3e,(byte)0xf1,(byte)0x01 })
+ .put(PPC32Registers.GPR14,
+ new byte[] { (byte)0xef,(byte)0x2e,0x26,(byte)0x91 })
+ .put(PPC32Registers.GPR15,
+ new byte[] { (byte)0x9c,(byte)0x1a,(byte)0x6e,(byte)0xe1 })
+ .put(PPC32Registers.GPR16,
+ new byte[] { (byte)0x20,(byte)0x0d,0x11,(byte)0x34 })
+ .put(PPC32Registers.GPR17,
+ new byte[] { (byte)0x63,(byte)0x4b,(byte)0x99,(byte)0x11 })
+ .put(PPC32Registers.GPR18,
+ new byte[] { (byte)0xd8,(byte)0x9b,(byte)0xde,(byte)0x81 })
+ .put(PPC32Registers.GPR19,
+ new byte[] { (byte)0x6e,(byte)0x6e,(byte)0xf9,(byte)0xba })
+ .put(PPC32Registers.GPR20,
+ new byte[] { (byte)0x55,(byte)0x51,(byte)0xaa,(byte)0xc3 })
+ .put(PPC32Registers.GPR21,
+ new byte[] { (byte)0x12,(byte)0x9c,(byte)0x72,(byte)0x3e })
+ .put(PPC32Registers.GPR22,
+ new byte[] { (byte)0x29,(byte)0x9c,(byte)0x77,(byte)0x33 })
+ .put(PPC32Registers.GPR23,
+ new byte[] { (byte)0x31,(byte)0x9c,0x20,(byte)0x44 })
+ .put(PPC32Registers.GPR24,
+ new byte[] { (byte)0xf3,(byte)0x9c,0x45,(byte)0xbb })
+ .put(PPC32Registers.GPR25,
+ new byte[] { (byte)0x10,(byte)0x9c,(byte)0x92,(byte)0xfa })
+ .put(PPC32Registers.GPR26,
+ new byte[] { (byte)0xe4,(byte)0x9c,(byte)0xbc,(byte)0xd8 })
+ .put(PPC32Registers.GPR27,
+ new byte[] { (byte)0x39,(byte)0x9c,(byte)0xe5,(byte)0xc6 })
+ .put(PPC32Registers.GPR28,
+ new byte[] { (byte)0x43,(byte)0x9c,(byte)0x4a,(byte)0x99 })
+ .put(PPC32Registers.GPR29,
+ new byte[] { (byte)0xd7,(byte)0x9c,0x44,(byte)0x01 })
+ .put(PPC32Registers.GPR30,
+ new byte[] { (byte)0x62,(byte)0x9c,0x09,(byte)0xeb })
+ .put(PPC32Registers.GPR31,
+ new byte[] { (byte)0x42,(byte)0x9c,0x78,(byte)0xa1 })
+
+ .put(PPC32Registers.FPR0,
+ new byte[] { (byte)0xa3,(byte)0x9c,0x20,(byte)0xd8,
+ (byte)0xe2,(byte)0xb4,0x7b,(byte)0x83 })
+ ;
+
+ private Values PPC64 = new Values()
+ .put(PPC64Registers.GPR0, // 0x837bb4e2d8209ca3
+ new byte[] { (byte)0xa3,(byte)0x9c,0x20,(byte)0xd8,
+ (byte)0xe2,(byte)0xb4,0x7b,(byte)0x83 })
+ ;
+
private final ISAMap isaValues = new ISAMap("RegsCase")
- .put(ISA.IA32, IA32).put(ISA.X8664, X8664)
+ .put(ISA.IA32, IA32)
+ .put(ISA.X8664, X8664)
+ .put(ISA.PPC32BE, PPC32)
+ .put(ISA.PPC64BE, PPC64)
;
}
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