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* [SCM] master: Lay the base for AltiVec register support.
@ 2008-04-15 22:39 bauermann
0 siblings, 0 replies; only message in thread
From: bauermann @ 2008-04-15 22:39 UTC (permalink / raw)
To: frysk-cvs
The branch, master has been updated
via 7fd681e8211332ed2f973456aa7add363f28183e (commit)
via 6daa50892246080c78e41bf8fa0ef6f717ea7286 (commit)
from 9a4f439eacad3c3f7c84c5bfe3cf5546c35572d8 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email.
- Log -----------------------------------------------------------------
commit 7fd681e8211332ed2f973456aa7add363f28183e
Author: Thiago Jung Bauermann <bauerman@br.ibm.com>
Date: Tue Apr 15 19:30:42 2008 -0300
Lay the base for AltiVec register support.
frysk-core/frysk/isa/banks/ChangeLog
2008-04-15 Thiago Jung Bauermann <bauerman@br.ibm.com>
* LinuxPPCRegisterBanks.java (VRREGS): Rename to ...
(VRREGS64): ... this, and add vr0 to vr31 registers.
* PPCBankRegisters.java (PPC64BE): Add VRREGS64.
frysk-core/frysk/isa/registers/ChangeLog
2008-04-15 Thiago Jung Bauermann <bauerman@br.ibm.com>
* PPC64Registers.java (VR0 to VR31): New.
(VECTOR): New.
(allRegs): Reorder, and add VECTOR.
(PPC64Registers): Reorder register groups, add VECTOR and remove ALL.
frysk-core/frysk/stack/ChangeLog
2008-04-15 Thiago Jung Bauermann <bauerman@br.ibm.com>
* LibunwindRegisterMapFactory.java (PPC64): Add AltiVec registers.
frysk-core/frysk/testbed/ChangeLog
2008-04-15 Thiago Jung Bauermann <bauerman@br.ibm.com>
* RegsCase.java (PPC64): Add values for AltiVec registers.
commit 6daa50892246080c78e41bf8fa0ef6f717ea7286
Author: Thiago Jung Bauermann <bauerman@br.ibm.com>
Date: Tue Apr 15 12:10:18 2008 -0300
Add DWARF register mapping for PowerPC64.
frysk-core/frysk/debuginfo/ChangeLog
2008-04-15 Thiago Jung Bauermann <bauerman@br.ibm.com>
* DwarfRegisterMapFactory.java (PPC64BE): New.
(isaToMap): Add PPC64BE.
frysk-sys/lib/dwfl/ChangeLog
2008-04-15 Thiago Jung Bauermann <bauerman@br.ibm.com>
* DwarfRegistersPPC64.mkenum: New.
-----------------------------------------------------------------------
Summary of changes:
frysk-core/frysk/debuginfo/ChangeLog | 5 +-
.../frysk/debuginfo/DwarfRegisterMapFactory.java | 76 +++++++++
frysk-core/frysk/isa/banks/ChangeLog | 6 +
.../frysk/isa/banks/LinuxPPCRegisterBanks.java | 54 ++++++--
frysk-core/frysk/isa/banks/PPCBankRegisters.java | 2 +
frysk-core/frysk/isa/registers/ChangeLog | 7 +
frysk-core/frysk/isa/registers/PPC64Registers.java | 111 +++++++++++++-
frysk-core/frysk/stack/ChangeLog | 4 +
.../frysk/stack/LibunwindRegisterMapFactory.java | 32 ++++
frysk-core/frysk/testbed/ChangeLog | 4 +
frysk-core/frysk/testbed/RegsCase.java | 160 ++++++++++++++++++++
frysk-sys/lib/dwfl/ChangeLog | 4 +
frysk-sys/lib/dwfl/DwarfRegistersPPC64.mkenum | 106 +++++++++++++
13 files changed, 550 insertions(+), 21 deletions(-)
create mode 100644 frysk-sys/lib/dwfl/DwarfRegistersPPC64.mkenum
First 500 lines of diff:
diff --git a/frysk-core/frysk/debuginfo/ChangeLog b/frysk-core/frysk/debuginfo/ChangeLog
index 0fd29e1..6d39d15 100644
--- a/frysk-core/frysk/debuginfo/ChangeLog
+++ b/frysk-core/frysk/debuginfo/ChangeLog
@@ -1,5 +1,8 @@
-2008-04-15 Sami Wagiaalla <swagiaal@redhat.com>
+2008-04-15 Thiago Jung Bauermann <bauerman@br.ibm.com>
+ * DwarfRegisterMapFactory.java (PPC64BE): New.
+ (isaToMap): Add PPC64BE.
+2008-04-15 Sami Wagiaalla <swagiaal@redhat.com>
* TestFrameDebugInfo.java: Replaced use of ConcreteFunction with
Function.
* DebugInfoStackFactory.java: Updated.
diff --git a/frysk-core/frysk/debuginfo/DwarfRegisterMapFactory.java b/frysk-core/frysk/debuginfo/DwarfRegisterMapFactory.java
index d9430bd..1c08493 100644
--- a/frysk-core/frysk/debuginfo/DwarfRegisterMapFactory.java
+++ b/frysk-core/frysk/debuginfo/DwarfRegisterMapFactory.java
@@ -41,11 +41,13 @@ package frysk.debuginfo;
import lib.dwfl.DwarfRegistersX86;
import lib.dwfl.DwarfRegistersX8664;
+import lib.dwfl.DwarfRegistersPPC64;
import frysk.isa.ISA;
import frysk.isa.ISAMap;
import frysk.isa.registers.IA32Registers;
import frysk.isa.registers.RegisterMap;
import frysk.isa.registers.X8664Registers;
+import frysk.isa.registers.PPC64Registers;
public class DwarfRegisterMapFactory {
@@ -82,10 +84,84 @@ public class DwarfRegisterMapFactory {
.add(X8664Registers.RIP, DwarfRegistersX8664.RIP)
;
+ private static final RegisterMap PPC64BE
+ = new RegisterMap("PowerPC64 DWARF")
+ .add(PPC64Registers.GPR0, DwarfRegistersPPC64.GPR0)
+ .add(PPC64Registers.GPR1, DwarfRegistersPPC64.GPR1)
+ .add(PPC64Registers.GPR2, DwarfRegistersPPC64.GPR2)
+ .add(PPC64Registers.GPR3, DwarfRegistersPPC64.GPR3)
+ .add(PPC64Registers.GPR4, DwarfRegistersPPC64.GPR4)
+ .add(PPC64Registers.GPR5, DwarfRegistersPPC64.GPR5)
+ .add(PPC64Registers.GPR6, DwarfRegistersPPC64.GPR6)
+ .add(PPC64Registers.GPR7, DwarfRegistersPPC64.GPR7)
+ .add(PPC64Registers.GPR8, DwarfRegistersPPC64.GPR8)
+ .add(PPC64Registers.GPR9, DwarfRegistersPPC64.GPR9)
+ .add(PPC64Registers.GPR10, DwarfRegistersPPC64.GPR10)
+ .add(PPC64Registers.GPR11, DwarfRegistersPPC64.GPR11)
+ .add(PPC64Registers.GPR12, DwarfRegistersPPC64.GPR12)
+ .add(PPC64Registers.GPR13, DwarfRegistersPPC64.GPR13)
+ .add(PPC64Registers.GPR14, DwarfRegistersPPC64.GPR14)
+ .add(PPC64Registers.GPR15, DwarfRegistersPPC64.GPR15)
+ .add(PPC64Registers.GPR16, DwarfRegistersPPC64.GPR16)
+ .add(PPC64Registers.GPR17, DwarfRegistersPPC64.GPR17)
+ .add(PPC64Registers.GPR18, DwarfRegistersPPC64.GPR18)
+ .add(PPC64Registers.GPR19, DwarfRegistersPPC64.GPR19)
+ .add(PPC64Registers.GPR20, DwarfRegistersPPC64.GPR20)
+ .add(PPC64Registers.GPR21, DwarfRegistersPPC64.GPR21)
+ .add(PPC64Registers.GPR22, DwarfRegistersPPC64.GPR22)
+ .add(PPC64Registers.GPR23, DwarfRegistersPPC64.GPR23)
+ .add(PPC64Registers.GPR24, DwarfRegistersPPC64.GPR24)
+ .add(PPC64Registers.GPR25, DwarfRegistersPPC64.GPR25)
+ .add(PPC64Registers.GPR26, DwarfRegistersPPC64.GPR26)
+ .add(PPC64Registers.GPR27, DwarfRegistersPPC64.GPR27)
+ .add(PPC64Registers.GPR28, DwarfRegistersPPC64.GPR28)
+ .add(PPC64Registers.GPR29, DwarfRegistersPPC64.GPR29)
+ .add(PPC64Registers.GPR30, DwarfRegistersPPC64.GPR30)
+ .add(PPC64Registers.GPR31, DwarfRegistersPPC64.GPR31)
+ .add(PPC64Registers.FPR0, DwarfRegistersPPC64.FPR0)
+ .add(PPC64Registers.FPR1, DwarfRegistersPPC64.FPR1)
+ .add(PPC64Registers.FPR2, DwarfRegistersPPC64.FPR2)
+ .add(PPC64Registers.FPR3, DwarfRegistersPPC64.FPR3)
+ .add(PPC64Registers.FPR4, DwarfRegistersPPC64.FPR4)
+ .add(PPC64Registers.FPR5, DwarfRegistersPPC64.FPR5)
+ .add(PPC64Registers.FPR6, DwarfRegistersPPC64.FPR6)
+ .add(PPC64Registers.FPR7, DwarfRegistersPPC64.FPR7)
+ .add(PPC64Registers.FPR8, DwarfRegistersPPC64.FPR8)
+ .add(PPC64Registers.FPR9, DwarfRegistersPPC64.FPR9)
+ .add(PPC64Registers.FPR10, DwarfRegistersPPC64.FPR10)
+ .add(PPC64Registers.FPR11, DwarfRegistersPPC64.FPR11)
+ .add(PPC64Registers.FPR12, DwarfRegistersPPC64.FPR12)
+ .add(PPC64Registers.FPR13, DwarfRegistersPPC64.FPR13)
+ .add(PPC64Registers.FPR14, DwarfRegistersPPC64.FPR14)
+ .add(PPC64Registers.FPR15, DwarfRegistersPPC64.FPR15)
+ .add(PPC64Registers.FPR16, DwarfRegistersPPC64.FPR16)
+ .add(PPC64Registers.FPR17, DwarfRegistersPPC64.FPR17)
+ .add(PPC64Registers.FPR18, DwarfRegistersPPC64.FPR18)
+ .add(PPC64Registers.FPR19, DwarfRegistersPPC64.FPR19)
+ .add(PPC64Registers.FPR20, DwarfRegistersPPC64.FPR20)
+ .add(PPC64Registers.FPR21, DwarfRegistersPPC64.FPR21)
+ .add(PPC64Registers.FPR22, DwarfRegistersPPC64.FPR22)
+ .add(PPC64Registers.FPR23, DwarfRegistersPPC64.FPR23)
+ .add(PPC64Registers.FPR24, DwarfRegistersPPC64.FPR24)
+ .add(PPC64Registers.FPR25, DwarfRegistersPPC64.FPR25)
+ .add(PPC64Registers.FPR26, DwarfRegistersPPC64.FPR26)
+ .add(PPC64Registers.FPR27, DwarfRegistersPPC64.FPR27)
+ .add(PPC64Registers.FPR28, DwarfRegistersPPC64.FPR28)
+ .add(PPC64Registers.FPR29, DwarfRegistersPPC64.FPR29)
+ .add(PPC64Registers.FPR30, DwarfRegistersPPC64.FPR30)
+ .add(PPC64Registers.FPR31, DwarfRegistersPPC64.FPR31)
+ .add(PPC64Registers.CCR, DwarfRegistersPPC64.CCR)
+ .add(PPC64Registers.FPSCR, DwarfRegistersPPC64.FPSCR)
+ .add(PPC64Registers.XER, DwarfRegistersPPC64.XER)
+ .add(PPC64Registers.LR, DwarfRegistersPPC64.LR)
+ .add(PPC64Registers.CTR, DwarfRegistersPPC64.CTR)
+ ;
+
private static final ISAMap isaToMap
= new ISAMap("DwarfRegisterMapFactory")
.put(ISA.IA32, IA32)
.put(ISA.X8664, X8664)
+ .put(ISA.PPC64BE, PPC64BE)
;
public static RegisterMap getRegisterMap(ISA isa) {
diff --git a/frysk-core/frysk/isa/banks/ChangeLog b/frysk-core/frysk/isa/banks/ChangeLog
index 57c0c11..d91d62c 100644
--- a/frysk-core/frysk/isa/banks/ChangeLog
+++ b/frysk-core/frysk/isa/banks/ChangeLog
@@ -1,3 +1,9 @@
+2008-04-15 Thiago Jung Bauermann <bauerman@br.ibm.com>
+
+ * LinuxPPCRegisterBanks.java (VRREGS): Rename to ...
+ (VRREGS64): ... this, and add vr0 to vr31 registers.
+ * PPCBankRegisters.java (PPC64BE): Add VRREGS64.
+
2008-04-09 Thiago Jung Bauermann <bauerman@br.ibm.com>
* PPCBankRegisters.java (PPC64BE): Fix bank indexes for GREGS64
diff --git a/frysk-core/frysk/isa/banks/LinuxPPCRegisterBanks.java b/frysk-core/frysk/isa/banks/LinuxPPCRegisterBanks.java
index 854ff7a..b2fd02b 100644
--- a/frysk-core/frysk/isa/banks/LinuxPPCRegisterBanks.java
+++ b/frysk-core/frysk/isa/banks/LinuxPPCRegisterBanks.java
@@ -79,7 +79,7 @@ public class LinuxPPCRegisterBanks {
.add(new BankRegister(116, 4, PPC32Registers.GPR29))
.add(new BankRegister(120, 4, PPC32Registers.GPR30))
.add(new BankRegister(124, 4, PPC32Registers.GPR31))
- .add(new BankRegister(128, 4, PPC32Registers.NIP)) //Fixme: PC I belive
+ .add(new BankRegister(128, 4, PPC32Registers.NIP)) //FIXME: PC I believe
.add(new BankRegister(132, 4, PPC32Registers.MSR))
.add(new BankRegister(136, 4, PPC32Registers.ORIGR3))
.add(new BankRegister(140, 4, PPC32Registers.CTR))
@@ -181,7 +181,7 @@ public class LinuxPPCRegisterBanks {
public static final BankRegisterMap FPREGS64
= new BankRegisterMap()
- .add(new BankRegister(384, 8, PPC64Registers.FPR0)) //PT_FPR0 48
+ .add(new BankRegister(384, 8, PPC64Registers.FPR0)) //PT_FPR0 48
.add(new BankRegister(392, 8, PPC64Registers.FPR1))
.add(new BankRegister(400, 8, PPC64Registers.FPR2))
.add(new BankRegister(408, 8, PPC64Registers.FPR3))
@@ -216,16 +216,48 @@ public class LinuxPPCRegisterBanks {
.add(new BankRegister(640, 4, PPC64Registers.FPSCR))
;
- public static final BankRegisterMap VRREGS
+ /*
+ * AltiVec Registers go in a separate notes section in core files, so I guess
+ * it makes sense to put them in a separate bank here.
+ */
+ public static final BankRegisterMap VRREGS64
= new BankRegisterMap()
- // Fixme: need to implement altivec registers
- // Vector Registers are 128 bit wide - in both PPC32 and PPC64
- //.add(new BankRegister(0, 656, 16, PPC64Registers.VR0)) PT_VR0 82
- //...
- //.add(new BankRegister(0, 1152, 16, PPC64Registers.V31)) PT_VR0 + 31*2), index 148
- //Need to put a 8 bytes pad here, because VSCR is 8 byte wide only
- .add(new BankRegister(1176, 8, PPC64Registers.VSCR)) // PT_VSCR (PT_VR0 + 32*2 + 1), index 147
- .add(new BankRegister(1184, 8, PPC64Registers.VRSAVE)) // PT_VRSAVE (PT_VR0 + 33*2), index 148
+ // Each Vector reg occupies 2 slots in 64-bit.
+ .add(new BankRegister(82*8, 16, PPC64Registers.VR0)) //PT_VR0 82
+ .add(new BankRegister(84*8, 16, PPC64Registers.VR1))
+ .add(new BankRegister(86*8, 16, PPC64Registers.VR2))
+ .add(new BankRegister(88*8, 16, PPC64Registers.VR3))
+ .add(new BankRegister(90*8, 16, PPC64Registers.VR4))
+ .add(new BankRegister(92*8, 16, PPC64Registers.VR5))
+ .add(new BankRegister(94*8, 16, PPC64Registers.VR6))
+ .add(new BankRegister(96*8, 16, PPC64Registers.VR7))
+ .add(new BankRegister(98*8, 16, PPC64Registers.VR8))
+ .add(new BankRegister(100*8, 16, PPC64Registers.VR9))
+ .add(new BankRegister(102*8, 16, PPC64Registers.VR10))
+ .add(new BankRegister(104*8, 16, PPC64Registers.VR11))
+ .add(new BankRegister(106*8, 16, PPC64Registers.VR12))
+ .add(new BankRegister(108*8, 16, PPC64Registers.VR13))
+ .add(new BankRegister(110*8, 16, PPC64Registers.VR14))
+ .add(new BankRegister(112*8, 16, PPC64Registers.VR15))
+ .add(new BankRegister(114*8, 16, PPC64Registers.VR16))
+ .add(new BankRegister(116*8, 16, PPC64Registers.VR17))
+ .add(new BankRegister(118*8, 16, PPC64Registers.VR18))
+ .add(new BankRegister(120*8, 16, PPC64Registers.VR19))
+ .add(new BankRegister(122*8, 16, PPC64Registers.VR20))
+ .add(new BankRegister(124*8, 16, PPC64Registers.VR21))
+ .add(new BankRegister(126*8, 16, PPC64Registers.VR22))
+ .add(new BankRegister(128*8, 16, PPC64Registers.VR23))
+ .add(new BankRegister(130*8, 16, PPC64Registers.VR24))
+ .add(new BankRegister(132*8, 16, PPC64Registers.VR25))
+ .add(new BankRegister(134*8, 16, PPC64Registers.VR26))
+ .add(new BankRegister(136*8, 16, PPC64Registers.VR27))
+ .add(new BankRegister(138*8, 16, PPC64Registers.VR28))
+ .add(new BankRegister(140*8, 16, PPC64Registers.VR29))
+ .add(new BankRegister(142*8, 16, PPC64Registers.VR30))
+ .add(new BankRegister(144*8, 16, PPC64Registers.VR31))
+ //Need to put a 8 bytes pad here, because VSCR is 8 byte wide only
+ .add(new BankRegister(147*8, 8, PPC64Registers.VSCR)) // PT_VSCR (PT_VR0 + 32*2 + 1), index 147
+ .add(new BankRegister(148*8, 8, PPC64Registers.VRSAVE)) // PT_VRSAVE (PT_VR0 + 33*2), index 148
;
}
diff --git a/frysk-core/frysk/isa/banks/PPCBankRegisters.java b/frysk-core/frysk/isa/banks/PPCBankRegisters.java
index 23dcaae..d1773b6 100644
--- a/frysk-core/frysk/isa/banks/PPCBankRegisters.java
+++ b/frysk-core/frysk/isa/banks/PPCBankRegisters.java
@@ -58,6 +58,8 @@ public class PPCBankRegisters {
= new BankArrayRegisterMap()
.add(0, LinuxPPCRegisterBanks.GREGS64)
.add(1, LinuxPPCRegisterBanks.FPREGS64)
+ // AltiVec registers go to a separate note section called NT_PPC_VMX
+ .add(2, LinuxPPCRegisterBanks.VRREGS64)
;
public static final BankArrayRegisterMap PPC32BE_ON_PPC64BE
diff --git a/frysk-core/frysk/isa/registers/ChangeLog b/frysk-core/frysk/isa/registers/ChangeLog
index 5ca7bbd..f6959f3 100644
--- a/frysk-core/frysk/isa/registers/ChangeLog
+++ b/frysk-core/frysk/isa/registers/ChangeLog
@@ -1,3 +1,10 @@
+2008-04-15 Thiago Jung Bauermann <bauerman@br.ibm.com>
+
+ * PPC64Registers.java (VR0 to VR31): New.
+ (VECTOR): New.
+ (allRegs): Reorder, and add VECTOR.
+ (PPC64Registers): Reorder register groups, add VECTOR and remove ALL.
+
2008-03-26 Phil Muldoon <pmuldoon@redhat.com>
* X8664Registers.java: Add debug register group.
diff --git a/frysk-core/frysk/isa/registers/PPC64Registers.java b/frysk-core/frysk/isa/registers/PPC64Registers.java
index afa59ef..a5505c4 100644
--- a/frysk-core/frysk/isa/registers/PPC64Registers.java
+++ b/frysk-core/frysk/isa/registers/PPC64Registers.java
@@ -248,8 +248,88 @@ public class PPC64Registers extends Registers {
public static final Register FPSCR
= new Register("fpscr", StandardTypes.INT32B_T);
+ /*
+ * Altivec (vector) registers.
+ *
+ * FIXME: The type of a vector register should be a union of the
+ * possible types that can be stored there, like in GDB:
+ *
+ * (gdb) ptype $vr0
+ * type = union __gdb_builtin_type_vec128 {
+ * int128_t uint128;
+ * float v4_float[4];
+ * int32_t v4_int32[4];
+ * int16_t v8_int16[8];
+ * int8_t v16_int8[16];
+ * }
+ */
+ public static final Register VR0
+ = new Register("vr0", StandardTypes.UINT128B_T);
+ public static final Register VR1
+ = new Register("vr1", StandardTypes.UINT128B_T);
+ public static final Register VR2
+ = new Register("vr2", StandardTypes.UINT128B_T);
+ public static final Register VR3
+ = new Register("vr3", StandardTypes.UINT128B_T);
+ public static final Register VR4
+ = new Register("vr4", StandardTypes.UINT128B_T);
+ public static final Register VR5
+ = new Register("vr5", StandardTypes.UINT128B_T);
+ public static final Register VR6
+ = new Register("vr6", StandardTypes.UINT128B_T);
+ public static final Register VR7
+ = new Register("vr7", StandardTypes.UINT128B_T);
+ public static final Register VR8
+ = new Register("vr8", StandardTypes.UINT128B_T);
+ public static final Register VR9
+ = new Register("vr9", StandardTypes.UINT128B_T);
+ public static final Register VR10
+ = new Register("vr10", StandardTypes.UINT128B_T);
+ public static final Register VR11
+ = new Register("vr11", StandardTypes.UINT128B_T);
+ public static final Register VR12
+ = new Register("vr12", StandardTypes.UINT128B_T);
+ public static final Register VR13
+ = new Register("vr13", StandardTypes.UINT128B_T);
+ public static final Register VR14
+ = new Register("vr14", StandardTypes.UINT128B_T);
+ public static final Register VR15
+ = new Register("vr15", StandardTypes.UINT128B_T);
+ public static final Register VR16
+ = new Register("vr16", StandardTypes.UINT128B_T);
+ public static final Register VR17
+ = new Register("vr17", StandardTypes.UINT128B_T);
+ public static final Register VR18
+ = new Register("vr18", StandardTypes.UINT128B_T);
+ public static final Register VR19
+ = new Register("vr19", StandardTypes.UINT128B_T);
+ public static final Register VR20
+ = new Register("vr20", StandardTypes.UINT128B_T);
+ public static final Register VR21
+ = new Register("vr21", StandardTypes.UINT128B_T);
+ public static final Register VR22
+ = new Register("vr22", StandardTypes.UINT128B_T);
+ public static final Register VR23
+ = new Register("vr23", StandardTypes.UINT128B_T);
+ public static final Register VR24
+ = new Register("vr24", StandardTypes.UINT128B_T);
+ public static final Register VR25
+ = new Register("vr25", StandardTypes.UINT128B_T);
+ public static final Register VR26
+ = new Register("vr26", StandardTypes.UINT128B_T);
+ public static final Register VR27
+ = new Register("vr27", StandardTypes.UINT128B_T);
+ public static final Register VR28
+ = new Register("vr28", StandardTypes.UINT128B_T);
+ public static final Register VR29
+ = new Register("vr29", StandardTypes.UINT128B_T);
+ public static final Register VR30
+ = new Register("vr30", StandardTypes.UINT128B_T);
+ public static final Register VR31
+ = new Register("vr31", StandardTypes.UINT128B_T);
+
/*
- * Alti-vec special registers
+ * Altivec special registers
*/
public static final Register VSCR
= new Register("vscr", StandardTypes.INT64B_T);
@@ -291,6 +371,14 @@ public class PPC64Registers extends Registers {
FPR20, FPR21, FPR22, FPR23, FPR24, FPR25, FPR26, FPR27, FPR28, FPR29,
FPR30, FPR31 });
+ public static final RegisterGroup VECTOR
+ = new RegisterGroup("vector",
+ new Register[] {
+ VR0 , VR1 , VR2 , VR3 , VR4 , VR5 , VR6 , VR7 , VR8 , VR9 ,
+ VR10, VR11, VR12, VR13, VR14, VR15, VR16, VR17, VR18, VR19,
+ VR20, VR21, VR22, VR23, VR24, VR25, VR26, VR27, VR28, VR29,
+ VR30, VR31 });
+
/*
* Creating the special ALL group
*/
@@ -298,21 +386,26 @@ public class PPC64Registers extends Registers {
static {
Register[] allRegs = new Register[
GENERAL.getRegisters().length +
- SPECIAL.getRegisters().length +
- FLOATING_POINTER.getRegisters().length];
+ FLOATING_POINTER.getRegisters().length +
+ VECTOR.getRegisters().length +
+ SPECIAL.getRegisters().length];
System.arraycopy(GENERAL.getRegisters(), 0,
allRegs, 0,
GENERAL.getRegisters().length);
- System.arraycopy(SPECIAL.getRegisters(), 0,
- allRegs, GENERAL.getRegisters().length,
- SPECIAL.getRegisters().length);
-
System.arraycopy(FLOATING_POINTER.getRegisters(), 0,
- allRegs, GENERAL.getRegisters().length + SPECIAL.getRegisters().length,
+ allRegs, GENERAL.getRegisters().length,
FLOATING_POINTER.getRegisters().length);
+ System.arraycopy(VECTOR.getRegisters(), 0,
+ allRegs, GENERAL.getRegisters().length + FLOATING_POINTER.getRegisters().length,
+ VECTOR.getRegisters().length);
+
+ System.arraycopy(SPECIAL.getRegisters(), 0,
+ allRegs, GENERAL.getRegisters().length + FLOATING_POINTER.getRegisters().length +
+ VECTOR.getRegisters().length, SPECIAL.getRegisters().length);
+
ALL = new RegisterGroup("all", allRegs);
}
@@ -336,6 +429,6 @@ public class PPC64Registers extends Registers {
* Default Constructor
*/
PPC64Registers() {
- super(new RegisterGroup[] { GENERAL, SPECIAL, FLOATING_POINTER, ALL });
+ super(new RegisterGroup[] { GENERAL, FLOATING_POINTER, VECTOR, SPECIAL });
}
}
diff --git a/frysk-core/frysk/stack/ChangeLog b/frysk-core/frysk/stack/ChangeLog
index da35a68..5f582a5 100644
--- a/frysk-core/frysk/stack/ChangeLog
+++ b/frysk-core/frysk/stack/ChangeLog
@@ -1,3 +1,7 @@
+2008-04-15 Thiago Jung Bauermann <bauerman@br.ibm.com>
+
+ * LibunwindRegisterMapFactory.java (PPC64): Add AltiVec registers.
+
2008-04-12 Mark Wielaard <mwielaard@redhat.com>
* TestFrame.java (testInnerFrameAddress): New test for bug #6029.
diff --git a/frysk-core/frysk/stack/LibunwindRegisterMapFactory.java b/frysk-core/frysk/stack/LibunwindRegisterMapFactory.java
index 576ce95..b20c864 100644
--- a/frysk-core/frysk/stack/LibunwindRegisterMapFactory.java
+++ b/frysk-core/frysk/stack/LibunwindRegisterMapFactory.java
@@ -195,6 +195,38 @@ public class LibunwindRegisterMapFactory {
.add(PPC64Registers.FPR29, UnwindRegistersPPC64.F29)
.add(PPC64Registers.FPR30, UnwindRegistersPPC64.F30)
.add(PPC64Registers.FPR31, UnwindRegistersPPC64.F31)
+ .add(PPC64Registers.VR0, UnwindRegistersPPC64.V0)
+ .add(PPC64Registers.VR1, UnwindRegistersPPC64.V1)
+ .add(PPC64Registers.VR2, UnwindRegistersPPC64.V2)
+ .add(PPC64Registers.VR3, UnwindRegistersPPC64.V3)
+ .add(PPC64Registers.VR4, UnwindRegistersPPC64.V4)
+ .add(PPC64Registers.VR5, UnwindRegistersPPC64.V5)
+ .add(PPC64Registers.VR6, UnwindRegistersPPC64.V6)
+ .add(PPC64Registers.VR7, UnwindRegistersPPC64.V7)
+ .add(PPC64Registers.VR8, UnwindRegistersPPC64.V8)
+ .add(PPC64Registers.VR9, UnwindRegistersPPC64.V9)
+ .add(PPC64Registers.VR10, UnwindRegistersPPC64.V10)
+ .add(PPC64Registers.VR11, UnwindRegistersPPC64.V11)
+ .add(PPC64Registers.VR12, UnwindRegistersPPC64.V12)
+ .add(PPC64Registers.VR13, UnwindRegistersPPC64.V13)
+ .add(PPC64Registers.VR14, UnwindRegistersPPC64.V14)
+ .add(PPC64Registers.VR15, UnwindRegistersPPC64.V15)
+ .add(PPC64Registers.VR16, UnwindRegistersPPC64.V16)
+ .add(PPC64Registers.VR17, UnwindRegistersPPC64.V17)
+ .add(PPC64Registers.VR18, UnwindRegistersPPC64.V18)
+ .add(PPC64Registers.VR19, UnwindRegistersPPC64.V19)
+ .add(PPC64Registers.VR20, UnwindRegistersPPC64.V20)
+ .add(PPC64Registers.VR21, UnwindRegistersPPC64.V21)
+ .add(PPC64Registers.VR22, UnwindRegistersPPC64.V22)
+ .add(PPC64Registers.VR23, UnwindRegistersPPC64.V23)
+ .add(PPC64Registers.VR24, UnwindRegistersPPC64.V24)
+ .add(PPC64Registers.VR25, UnwindRegistersPPC64.V25)
+ .add(PPC64Registers.VR26, UnwindRegistersPPC64.V26)
+ .add(PPC64Registers.VR27, UnwindRegistersPPC64.V27)
+ .add(PPC64Registers.VR28, UnwindRegistersPPC64.V28)
+ .add(PPC64Registers.VR29, UnwindRegistersPPC64.V29)
+ .add(PPC64Registers.VR30, UnwindRegistersPPC64.V30)
+ .add(PPC64Registers.VR31, UnwindRegistersPPC64.V31)
;
private static final RegisterMap PPC32
diff --git a/frysk-core/frysk/testbed/ChangeLog b/frysk-core/frysk/testbed/ChangeLog
index 9c2d310..e309525 100644
--- a/frysk-core/frysk/testbed/ChangeLog
+++ b/frysk-core/frysk/testbed/ChangeLog
@@ -1,3 +1,7 @@
+2008-04-15 Thiago Jung Bauermann <bauerman@br.ibm.com>
+
+ * RegsCase.java (PPC64): Add values for AltiVec registers.
+
2008-03-17 Andrew Cagney <cagney@redhat.com>
* CoredumpAction.java: Extend ProcBlockObserver.
diff --git a/frysk-core/frysk/testbed/RegsCase.java b/frysk-core/frysk/testbed/RegsCase.java
index ca97ca0..2a76ea9 100644
--- a/frysk-core/frysk/testbed/RegsCase.java
+++ b/frysk-core/frysk/testbed/RegsCase.java
@@ -868,6 +868,166 @@ public abstract class RegsCase extends TestLib {
.put(PPC64Registers.FPR31, // 0x5ee6e7418fe61e98
new byte[] { 0x5e,(byte)0xe6,(byte)0xe7,0x41,
(byte)0x8f,(byte)0xe6,0x1e,(byte)0x98 })
+ .put(PPC64Registers.VR0, // 0x44be6c17f1b7a38cfd16c678bd309d01
+ new byte[] { 0x44,(byte)0xbe,0x6c,0x17,
+ (byte)0xf1,(byte)0xb7,(byte)0xa3,(byte)0x8c,
+ (byte)0xfd,0x16,(byte)0xc6,0x78,
+ (byte)0xbd,0x30,(byte)0x9d,0x1 })
+ .put(PPC64Registers.VR1, // 0x4b8eacb677c1b42990652f9565244b3c
+ new byte[] { 0x4b,(byte)0x8e,(byte)0xac,(byte)0xb6,
+ 0x77,(byte)0xc1,(byte)0xb4,0x29,
+ (byte)0x90,0x65,0x2f,(byte)0x95,
+ 0x65,0x24,0x4b,0x3c })
+ .put(PPC64Registers.VR2, // 0x7696c4b4a91b0758114622c33bd5fbaa
+ new byte[] { 0x76,(byte)0x96,(byte)0xc4,(byte)0xb4,
+ (byte)0xa9,0x1b,0x7,0x58,
+ 0x11,0x46,0x22,(byte)0xc3,
+ 0x3b,(byte)0xd5,(byte)0xfb,(byte)0xaa })
+ .put(PPC64Registers.VR3, // 0x45a67a61b2ab6d7e51d42597b4582196
+ new byte[] { 0x45,(byte)0xa6,0x7a,0x61,
+ (byte)0xb2,(byte)0xab,0x6d,0x7e,
+ 0x51,(byte)0xd4,0x25,(byte)0x97,
+ (byte)0xb4,0x58,0x21,(byte)0x96 })
+ .put(PPC64Registers.VR4, // 0x58fc57e626059d0facdf5aa4b0d61f65
+ new byte[] { 0x58,(byte)0xfc,0x57,(byte)0xe6,
+ 0x26,0x5,(byte)0x9d,0xf,
+ (byte)0xac,(byte)0xdf,0x5a,(byte)0xa4,
+ (byte)0xb0,(byte)0xd6,0x1f,0x65 })
+ .put(PPC64Registers.VR5, // 0xccea5f417e175fa0307ad03de0a7746a
+ new byte[] { (byte)0xcc,(byte)0xea,0x5f,0x41,
+ 0x7e,0x17,0x5f,(byte)0xa0,
+ 0x30,0x7a,(byte)0xd0,0x3d,
+ (byte)0xe0,(byte)0xa7,0x74,0x6a })
+ .put(PPC64Registers.VR6, // 0x98b48dbbd61358bf24d173da255dc92
+ new byte[] { 0x9,(byte)0x8b,0x48,(byte)0xdb,
+ (byte)0xbd,0x61,0x35,(byte)0x8b,
+ (byte)0xf2,0x4d,0x17,0x3d,
+ (byte)0xa2,0x55,(byte)0xdc,(byte)0x92 })
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2008-04-15 22:39 [SCM] master: Lay the base for AltiVec register support bauermann
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