From mboxrd@z Thu Jan  1 00:00:00 1970
From: Joel Sherrill <joel@merlin.gcs.redstone.army.mil>
To: gas2@cygnus.com
Subject: Maximum Alignment Restrictions
Date: Thu, 11 Jan 1996 09:41:00 -0000
Message-id: <Pine.SV4.3.91.960111113044.4093B-100000@merlin>
X-SW-Source: 1996/msg00000.html

What is the rationale for the maximum alignment supported on a particular 
CPU family?  

My current problem is that the SPARC trap table must be on a 4K boundary
but that appears to be too large. 

My thinking is that there is no particular reason (except object format 
limitations) to place a CPU dependent limit on maximum alignment boundary.

Just curious.

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