[Bug c/11965] New: On SPARC, gcc produces invalid assembler code for a shift << 32 operation

["jk at tools dot de" <gcc-bugzilla@gcc.gnu.org>]

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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11965

           Summary: On SPARC, gcc produces invalid assembler code for a
                    shift << 32 operation
           Product: gcc
           Version: 3.3
            Status: UNCONFIRMED
          Severity: normal
          Priority: P2
         Component: c
        AssignedTo: unassigned at gcc dot gnu dot org
        ReportedBy: jk at tools dot de
                CC: gcc-bugs at gcc dot gnu dot org
 GCC build triplet: sparc-sun-solaris2.8
  GCC host triplet: sparc-sun-solaris2.8
GCC target triplet: sparc-sun-solaris2.8

GCC 3.3 on Solaris SPARC produces invalid assembler code, for shift operator
shifting 32 bits.

GCC 3.3 is compiled to use the system's assembler, /usr/ccs/bin/as


To reproduce the issue (admitted, this code has undefined behaviour):

% cat shift.c

#if __GNUC__
#define ATTR_ALWAYS_INLINE __attribute__ ((__always_inline__))
#else
#define ATTR_ALWAYS_INLINE
#endif


static ATTR_ALWAYS_INLINE unsigned
put_bits(int n, unsigned int value)
{
        return value << n;
}

main()
{
        unsigned val = 1;
        int i;

        for (i = 0; i < 4; i++)
                val = put_bits(32, val);

        printf("val=%x\n", val);
}

% gcc -O3 -mcpu=ultrasparc -o shift shift.c
/usr/ccs/bin/as: "/tmp/cc0VFu29.s", line 20: error: shift count negative or too
big: 32


Looking at the generated assembler source...

% gcc -O3 -mcpu=ultrasparc -S shift.c

... there's a shift instruction with a constant shift count of 32, where the
immediate shift count is restricted to the range 0 .. 31 on SPARC:

       sll     %o1, 32, %o1


The same code used to compile with gcc 3.2 and erlier, and it does compile with
gcc 3.3 at optimization level -O2 or when option -mcpu=ultrasparc is not used.