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From: "dave at hiauly1 dot hia dot nrc dot ca" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug optimization/13424] [3.4/3.5 Regression] gcc.dg/20031202-1.c is miscompiled
Date: Mon, 05 Apr 2004 16:24:00 -0000 [thread overview]
Message-ID: <20040405162441.25898.qmail@sources.redhat.com> (raw)
In-Reply-To: <20031218033126.13424.danglin@gcc.gnu.org>
------- Additional Comments From dave at hiauly1 dot hia dot nrc dot ca 2004-04-05 16:24 -------
Subject: Re: [3.4/3.5 Regression] gcc.dg/20031202-1.c
> It ought to be fixed on gcc-3_4-branch only ATM (no trunk yet) and
> not on HPPA which has buggy backend, see:
> http://gcc.gnu.org/ml/gcc-patches/2004-04/msg00186.html
With the enclosed patch, the regression introduced by Jakub's fix
for this PR is fixed (c/14828). I confirm that the problem reported
in this PR is also fixed. I also don't see the failure on the 3.5 branch
anymore when the enclosed patch is installed. The patch also fixes the
Ada bootstrap problem reported in 14462. If this patch is approved,
I would like to close 13424, 14462 and 14828.
If there are remaining issues with RTX_UNCHANGING_P on 3.5, I think
they should be placed in a new PR.
The enclosed patch has been tested on hppa-unknown-linux-gnu (3.4.0, 3.5.0),
hppa2.0w-hp-hpux11.00 (3.4), hppa64-hp-hpux11.00 (3.4) and hppa64-hp-hpux11.11
(3.5 c only) with no observed regressions.
Mark, is this ok for 3.4?
I very much appreciate all the work that Jakub did in resolving this
problem. I just extended and tested what he had done.
Hopefully, this closes the long saga in reworking movstrsi.
Dave
--
J. David Anglin dave.anglin@nrc-cnrc.gc.ca
National Research Council of Canada (613) 990-0752 (FAX: 952-6602)
2004-04-05 Jakub Jelinek <jakuB@redhat.com>
John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
PR optimization/13424 (hppa), bootstrap/14462, c/14828
* pa.md: Use replace_equiv_address to retain the attributes of the
memory operands used in the split and peephole2 patterns for optimizing
the pre-reload movstrsi, movstrdi, clrstrsi and clrstrdi patterns.
Index: pa.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/pa/pa.md,v
retrieving revision 1.138.4.4
diff -u -3 -p -r1.138.4.4 pa.md
--- pa.md 6 Mar 2004 19:55:09 -0000 1.138.4.4
+++ pa.md 3 Apr 2004 17:03:15 -0000
@@ -3206,8 +3204,8 @@
[(set_attr "type" "multi,multi")])
(define_split
- [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
- (mem:BLK (match_operand:SI 1 "register_operand" "")))
+ [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" ""))
(clobber (match_operand:SI 2 "register_operand" ""))
(clobber (match_operand:SI 3 "register_operand" ""))
(clobber (match_operand:SI 6 "register_operand" ""))
@@ -3215,10 +3213,14 @@
(clobber (match_operand:SI 8 "register_operand" ""))
(use (match_operand:SI 4 "arith_operand" ""))
(use (match_operand:SI 5 "const_int_operand" ""))])]
- "!TARGET_64BIT && reload_completed && !flag_peephole2"
- [(set (match_dup 7) (match_dup 0))
- (set (match_dup 8) (match_dup 1))
- (parallel [(set (mem:BLK (match_dup 7)) (mem:BLK (match_dup 8)))
+ "!TARGET_64BIT && reload_completed && !flag_peephole2
+ && GET_CODE (operands[0]) == MEM
+ && register_operand (XEXP (operands[0], 0), SImode)
+ && GET_CODE (operands[1]) == MEM
+ && register_operand (XEXP (operands[1], 0), SImode)"
+ [(set (match_dup 7) (match_dup 9))
+ (set (match_dup 8) (match_dup 10))
+ (parallel [(set (match_dup 0) (match_dup 1))
(clobber (match_dup 2))
(clobber (match_dup 3))
(clobber (match_dup 6))
@@ -3227,11 +3229,17 @@
(use (match_dup 4))
(use (match_dup 5))
(const_int 0)])]
- "")
+ "
+{
+ operands[9] = XEXP (operands[0], 0);
+ operands[10] = XEXP (operands[1], 0);
+ operands[0] = replace_equiv_address (operands[0], operands[7]);
+ operands[1] = replace_equiv_address (operands[1], operands[8]);
+}")
(define_peephole2
- [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
- (mem:BLK (match_operand:SI 1 "register_operand" "")))
+ [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" ""))
(clobber (match_operand:SI 2 "register_operand" ""))
(clobber (match_operand:SI 3 "register_operand" ""))
(clobber (match_operand:SI 6 "register_operand" ""))
@@ -3239,8 +3247,12 @@
(clobber (match_operand:SI 8 "register_operand" ""))
(use (match_operand:SI 4 "arith_operand" ""))
(use (match_operand:SI 5 "const_int_operand" ""))])]
- "!TARGET_64BIT"
- [(parallel [(set (mem:BLK (match_dup 7)) (mem:BLK (match_dup 8)))
+ "!TARGET_64BIT
+ && GET_CODE (operands[0]) == MEM
+ && register_operand (XEXP (operands[0], 0), SImode)
+ && GET_CODE (operands[1]) == MEM
+ && register_operand (XEXP (operands[1], 0), SImode)"
+ [(parallel [(set (match_dup 0) (match_dup 1))
(clobber (match_dup 2))
(clobber (match_dup 3))
(clobber (match_dup 6))
@@ -3251,15 +3263,23 @@
(const_int 0)])]
"
{
- if (dead_or_set_p (curr_insn, operands[0]))
- operands[7] = operands[0];
+ rtx addr = XEXP (operands[0], 0);
+ if (dead_or_set_p (curr_insn, addr))
+ operands[7] = addr;
else
- emit_insn (gen_rtx_SET (VOIDmode, operands[7], operands[0]));
+ {
+ emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
+ operands[0] = replace_equiv_address (operands[0], operands[7]);
+ }
- if (dead_or_set_p (curr_insn, operands[1]))
- operands[8] = operands[1];
+ addr = XEXP (operands[1], 0);
+ if (dead_or_set_p (curr_insn, addr))
+ operands[8] = addr;
else
- emit_insn (gen_rtx_SET (VOIDmode, operands[8], operands[1]));
+ {
+ emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
+ operands[1] = replace_equiv_address (operands[1], operands[8]);
+ }
}")
(define_insn "movstrsi_postreload"
@@ -3372,8 +3392,8 @@
[(set_attr "type" "multi,multi")])
(define_split
- [(parallel [(set (mem:BLK (match_operand:DI 0 "register_operand" ""))
- (mem:BLK (match_operand:DI 1 "register_operand" "")))
+ [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" ""))
(clobber (match_operand:DI 2 "register_operand" ""))
(clobber (match_operand:DI 3 "register_operand" ""))
(clobber (match_operand:DI 6 "register_operand" ""))
@@ -3381,10 +3401,14 @@
(clobber (match_operand:DI 8 "register_operand" ""))
(use (match_operand:DI 4 "arith_operand" ""))
(use (match_operand:DI 5 "const_int_operand" ""))])]
- "TARGET_64BIT && reload_completed && !flag_peephole2"
- [(set (match_dup 7) (match_dup 0))
- (set (match_dup 8) (match_dup 1))
- (parallel [(set (mem:BLK (match_dup 7)) (mem:BLK (match_dup 8)))
+ "TARGET_64BIT && reload_completed && !flag_peephole2
+ && GET_CODE (operands[0]) == MEM
+ && register_operand (XEXP (operands[0], 0), DImode)
+ && GET_CODE (operands[1]) == MEM
+ && register_operand (XEXP (operands[1], 0), DImode)"
+ [(set (match_dup 7) (match_dup 9))
+ (set (match_dup 8) (match_dup 10))
+ (parallel [(set (match_dup 0) (match_dup 1))
(clobber (match_dup 2))
(clobber (match_dup 3))
(clobber (match_dup 6))
@@ -3393,11 +3417,17 @@
(use (match_dup 4))
(use (match_dup 5))
(const_int 0)])]
- "")
+ "
+{
+ operands[9] = XEXP (operands[0], 0);
+ operands[10] = XEXP (operands[1], 0);
+ operands[0] = replace_equiv_address (operands[0], operands[7]);
+ operands[1] = replace_equiv_address (operands[1], operands[8]);
+}")
(define_peephole2
- [(parallel [(set (mem:BLK (match_operand:DI 0 "register_operand" ""))
- (mem:BLK (match_operand:DI 1 "register_operand" "")))
+ [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" ""))
(clobber (match_operand:DI 2 "register_operand" ""))
(clobber (match_operand:DI 3 "register_operand" ""))
(clobber (match_operand:DI 6 "register_operand" ""))
@@ -3405,8 +3435,12 @@
(clobber (match_operand:DI 8 "register_operand" ""))
(use (match_operand:DI 4 "arith_operand" ""))
(use (match_operand:DI 5 "const_int_operand" ""))])]
- "TARGET_64BIT"
- [(parallel [(set (mem:BLK (match_dup 7)) (mem:BLK (match_dup 8)))
+ "TARGET_64BIT
+ && GET_CODE (operands[0]) == MEM
+ && register_operand (XEXP (operands[0], 0), DImode)
+ && GET_CODE (operands[1]) == MEM
+ && register_operand (XEXP (operands[1], 0), DImode)"
+ [(parallel [(set (match_dup 0) (match_dup 1))
(clobber (match_dup 2))
(clobber (match_dup 3))
(clobber (match_dup 6))
@@ -3417,15 +3451,23 @@
(const_int 0)])]
"
{
- if (dead_or_set_p (curr_insn, operands[0]))
- operands[7] = operands[0];
+ rtx addr = XEXP (operands[0], 0);
+ if (dead_or_set_p (curr_insn, addr))
+ operands[7] = addr;
else
- emit_insn (gen_rtx_SET (VOIDmode, operands[7], operands[0]));
+ {
+ emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
+ operands[0] = replace_equiv_address (operands[0], operands[7]);
+ }
- if (dead_or_set_p (curr_insn, operands[1]))
- operands[8] = operands[1];
+ addr = XEXP (operands[1], 0);
+ if (dead_or_set_p (curr_insn, addr))
+ operands[8] = addr;
else
- emit_insn (gen_rtx_SET (VOIDmode, operands[8], operands[1]));
+ {
+ emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
+ operands[1] = replace_equiv_address (operands[1], operands[8]);
+ }
}")
(define_insn "movstrdi_postreload"
@@ -3491,31 +3533,39 @@
[(set_attr "type" "multi,multi")])
(define_split
- [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
+ [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
(const_int 0))
(clobber (match_operand:SI 1 "register_operand" ""))
(clobber (match_operand:SI 4 "register_operand" ""))
(use (match_operand:SI 2 "arith_operand" ""))
(use (match_operand:SI 3 "const_int_operand" ""))])]
- "!TARGET_64BIT && reload_completed && !flag_peephole2"
- [(set (match_dup 4) (match_dup 0))
- (parallel [(set (mem:BLK (match_dup 4)) (const_int 0))
+ "!TARGET_64BIT && reload_completed && !flag_peephole2
+ && GET_CODE (operands[0]) == MEM
+ && register_operand (XEXP (operands[0], 0), SImode)"
+ [(set (match_dup 4) (match_dup 5))
+ (parallel [(set (match_dup 0) (const_int 0))
(clobber (match_dup 1))
(clobber (match_dup 4))
(use (match_dup 2))
(use (match_dup 3))
(const_int 0)])]
- "")
+ "
+{
+ operands[5] = XEXP (operands[0], 0);
+ operands[0] = replace_equiv_address (operands[0], operands[4]);
+}")
(define_peephole2
- [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
+ [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
(const_int 0))
(clobber (match_operand:SI 1 "register_operand" ""))
(clobber (match_operand:SI 4 "register_operand" ""))
(use (match_operand:SI 2 "arith_operand" ""))
(use (match_operand:SI 3 "const_int_operand" ""))])]
- "!TARGET_64BIT"
- [(parallel [(set (mem:BLK (match_dup 4)) (const_int 0))
+ "!TARGET_64BIT
+ && GET_CODE (operands[0]) == MEM
+ && register_operand (XEXP (operands[0], 0), SImode)"
+ [(parallel [(set (match_dup 0) (const_int 0))
(clobber (match_dup 1))
(clobber (match_dup 4))
(use (match_dup 2))
@@ -3523,10 +3573,14 @@
(const_int 0)])]
"
{
- if (dead_or_set_p (curr_insn, operands[0]))
- operands[4] = operands[0];
+ rtx addr = XEXP (operands[0], 0);
+ if (dead_or_set_p (curr_insn, addr))
+ operands[4] = addr;
else
- emit_insn (gen_rtx_SET (VOIDmode, operands[4], operands[0]));
+ {
+ emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
+ operands[0] = replace_equiv_address (operands[0], operands[4]);
+ }
}")
(define_insn "clrstrsi_postreload"
@@ -3589,31 +3643,39 @@
[(set_attr "type" "multi,multi")])
(define_split
- [(parallel [(set (mem:BLK (match_operand:DI 0 "register_operand" ""))
+ [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
(const_int 0))
(clobber (match_operand:DI 1 "register_operand" ""))
(clobber (match_operand:DI 4 "register_operand" ""))
(use (match_operand:DI 2 "arith_operand" ""))
(use (match_operand:DI 3 "const_int_operand" ""))])]
- "TARGET_64BIT && reload_completed && !flag_peephole2"
- [(set (match_dup 4) (match_dup 0))
- (parallel [(set (mem:BLK (match_dup 4)) (const_int 0))
+ "TARGET_64BIT && reload_completed && !flag_peephole2
+ && GET_CODE (operands[0]) == MEM
+ && register_operand (XEXP (operands[0], 0), DImode)"
+ [(set (match_dup 4) (match_dup 5))
+ (parallel [(set (match_dup 0) (const_int 0))
(clobber (match_dup 1))
(clobber (match_dup 4))
(use (match_dup 2))
(use (match_dup 3))
(const_int 0)])]
- "")
+ "
+{
+ operands[5] = XEXP (operands[0], 0);
+ operands[0] = replace_equiv_address (operands[0], operands[4]);
+}")
(define_peephole2
- [(parallel [(set (mem:BLK (match_operand:DI 0 "register_operand" ""))
+ [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
(const_int 0))
(clobber (match_operand:DI 1 "register_operand" ""))
(clobber (match_operand:DI 4 "register_operand" ""))
(use (match_operand:DI 2 "arith_operand" ""))
(use (match_operand:DI 3 "const_int_operand" ""))])]
- "TARGET_64BIT"
- [(parallel [(set (mem:BLK (match_dup 4)) (const_int 0))
+ "TARGET_64BIT
+ && GET_CODE (operands[0]) == MEM
+ && register_operand (XEXP (operands[0], 0), DImode)"
+ [(parallel [(set (match_dup 0) (const_int 0))
(clobber (match_dup 1))
(clobber (match_dup 4))
(use (match_dup 2))
@@ -3621,10 +3683,14 @@
(const_int 0)])]
"
{
- if (dead_or_set_p (curr_insn, operands[0]))
- operands[4] = operands[0];
+ rtx addr = XEXP (operands[0], 0);
+ if (dead_or_set_p (curr_insn, addr))
+ operands[4] = addr;
else
- emit_insn (gen_rtx_SET (VOIDmode, operands[4], operands[0]));
+ {
+ emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
+ operands[0] = replace_equiv_address (operands[0], operands[4]);
+ }
}")
(define_insn "clrstrdi_postreload"
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=13424
next prev parent reply other threads:[~2004-04-05 16:24 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-12-18 5:22 [Bug pending/13424] New: 20031202-1.c is miscompiled on all PA ports danglin at gcc dot gnu dot org
2003-12-18 5:25 ` [Bug optimization/13424] [3.4 Regression] " pinskia at gcc dot gnu dot org
2003-12-18 16:39 ` [Bug optimization/13424] [3.4 Regression] gcc.dg/20031202-1.c is miscompiled ebotcazou at gcc dot gnu dot org
2003-12-18 19:41 ` dave at hiauly1 dot hia dot nrc dot ca
2003-12-18 20:12 ` ebotcazou at gcc dot gnu dot org
2004-01-10 7:01 ` pinskia at gcc dot gnu dot org
2004-01-10 7:14 ` pinskia at gcc dot gnu dot org
2004-01-10 20:56 ` dave at hiauly1 dot hia dot nrc dot ca
2004-01-10 21:00 ` dave at hiauly1 dot hia dot nrc dot ca
2004-01-10 21:43 ` ebotcazou at gcc dot gnu dot org
2004-01-13 11:40 ` ebotcazou at gcc dot gnu dot org
2004-01-13 11:46 ` ebotcazou at gcc dot gnu dot org
2004-01-25 17:00 ` [Bug optimization/13424] [3.4/3.5 " schwab at suse dot de
2004-01-29 8:06 ` cvs-commit at gcc dot gnu dot org
2004-02-07 9:55 ` ebotcazou at gcc dot gnu dot org
2004-02-10 18:08 ` [Bug optimization/13424] [3.4 " cvs-commit at gcc dot gnu dot org
2004-02-10 20:34 ` pinskia at gcc dot gnu dot org
2004-02-21 23:34 ` danglin at gcc dot gnu dot org
2004-02-23 8:53 ` ebotcazou at gcc dot gnu dot org
2004-02-23 8:53 ` ebotcazou at gcc dot gnu dot org
2004-02-28 11:26 ` cvs-commit at gcc dot gnu dot org
2004-03-02 23:43 ` [Bug optimization/13424] [3.4/3.5 " rth at gcc dot gnu dot org
2004-03-03 0:58 ` dave at hiauly1 dot hia dot nrc dot ca
2004-03-16 21:18 ` ebotcazou at gcc dot gnu dot org
2004-03-16 21:23 ` ebotcazou at gcc dot gnu dot org
2004-03-17 3:21 ` dave at hiauly1 dot hia dot nrc dot ca
2004-03-17 10:13 ` ebotcazou at gcc dot gnu dot org
2004-03-17 17:57 ` ebotcazou at gcc dot gnu dot org
2004-03-18 2:13 ` dave at hiauly1 dot hia dot nrc dot ca
2004-03-27 16:10 ` cvs-commit at gcc dot gnu dot org
2004-04-02 23:06 ` cvs-commit at gcc dot gnu dot org
2004-04-05 7:46 ` steven at gcc dot gnu dot org
2004-04-05 15:35 ` jakub at gcc dot gnu dot org
2004-04-05 16:24 ` dave at hiauly1 dot hia dot nrc dot ca [this message]
2004-04-05 16:41 ` cvs-commit at gcc dot gnu dot org
2004-04-05 17:58 ` ebotcazou at gcc dot gnu dot org
2004-04-06 8:52 ` mark at codesourcery dot com
2004-04-06 9:04 ` cvs-commit at gcc dot gnu dot org
2004-04-06 16:05 ` danglin at gcc dot gnu dot org
2004-04-06 16:16 ` bangerth at dealii dot org
2004-04-06 16:20 ` dave at hiauly1 dot hia dot nrc dot ca
2004-04-06 17:53 ` bangerth at dealii dot org
2004-04-06 18:08 ` dave at hiauly1 dot hia dot nrc dot ca
2004-04-06 20:44 ` bangerth at dealii dot org
2004-04-13 20:42 ` cvs-commit at gcc dot gnu dot org
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