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From: "stuart at apple dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/18019] [4.0 Regression] -march=pentium4 generates word fetch instead of byte fetch
Date: Thu, 02 Dec 2004 01:08:00 -0000	[thread overview]
Message-ID: <20041202010755.12209.qmail@sourceware.org> (raw)
In-Reply-To: <20041015180025.18019.stuart@apple.com>


------- Additional Comments From stuart at apple dot com  2004-12-02 01:07 -------
Jan emailed this to me privately.  Appended here for completeness.  - stuart
----------------------------------------------------------------
Just to clarify things a bit.  TARGET_MOVX and
TARGET_PARTIAL_REG_DEPENDENCY is not about supporting some feature but
about a way the CPU deals with dependencies on partial registers.  Some
CPUs (Athlon+,P4+) deal with partial register writes as read-modify
operation of the whole thing (TARGET_PARTIAL_REG_DEPENDENCT) and for
some of these it is profitable to do dummy zero extend (TARGET_MOVX)
instead of loads to avoid the dependency, while others (K6, P3) give it
another internal name and don't see the false dependency
(TARGET_PARTIAL_REG_STALL). On the other hand they get penalty if the
result is used as a whole register.  There is unlikely to be ever CPU
spoiled up in both directions..

However the Roger's patch, as I understand it, is about avoiding movx as
it encodes longer on -Os.  It seems to me that for targets not defining
TARGET_PARTIAL_REG_STALL/TARGET_PARTIAL_REG_DEPENDENCY we should always
produce the straighforward movq as expected, while for
TARGET_PARTIAL_REG_STALL/TARGET_PARTIAL_REG_DEPENDENCY we can still use
the full moves as long as they don't encode longer.  I can't check right
now, but i believe it is only the movl imm, register that comes out
longer and that is the alternative 2.

We can also probably kill the TARGET_QIMODE_MATH as it is no longer
used.

There is the type and mode argument not only to choose the particular
instruction but also to drive scheduling (K6 for instance has limited
supply of units that do 8bit operations).  imovx is 32bit operation so
it needs to get SImode.  I would simply break out the alternative 2 from
both conditionals and would additionally check optimize_size to be
nonzero

I can prepare patch later next week unless someone beats me :)

Honza

-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=18019


  parent reply	other threads:[~2004-12-02  1:08 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2004-10-15 18:00 [Bug c/18019] New: " stuart at apple dot com
2004-10-15 18:05 ` [Bug c/18019] " stuart at apple dot com
2004-10-15 18:12 ` [Bug target/18019] " pinskia at gcc dot gnu dot org
2004-10-15 18:23 ` pinskia at gcc dot gnu dot org
2004-10-15 18:27 ` stuart at apple dot com
2004-10-15 18:36 ` [Bug target/18019] [4.0 Regression] " pinskia at gcc dot gnu dot org
2004-10-28 15:19 ` steven at gcc dot gnu dot org
2004-10-28 15:22 ` steven at gcc dot gnu dot org
2004-11-09  4:50 ` pinskia at gcc dot gnu dot org
2004-11-09 18:10 ` roger at eyesopen dot com
2004-11-09 19:34 ` stuart at apple dot com
2004-11-09 20:56 ` roger at eyesopen dot com
2004-11-16 19:40 ` stuart at apple dot com
2004-11-27 18:28 ` neroden at gcc dot gnu dot org
2004-12-02  1:08 ` stuart at apple dot com [this message]
2004-12-02  3:35 ` neroden at gcc dot gnu dot org
2004-12-02  9:02 ` jh at suse dot cz
2004-12-10 17:09 ` neroden at gcc dot gnu dot org
2004-12-18 22:49 ` steven at gcc dot gnu dot org
2004-12-19 16:16 ` jh at suse dot cz
2004-12-19 19:58 ` pinskia at gcc dot gnu dot org
2004-12-22 12:20 ` steven at gcc dot gnu dot org
2004-12-30 13:16 ` cvs-commit at gcc dot gnu dot org
2004-12-30 13:21 ` steven at gcc dot gnu dot org

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