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From: "amodra at bigpond dot net dot au" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/19147] New: invalid rlwinm patterns Date: Fri, 24 Dec 2004 06:25:00 -0000 [thread overview] Message-ID: <20041224062552.19147.amodra@bigpond.net.au> (raw) andsi3_internal7 and andsi3_internal8 generate invalid LT and GT condition codes. This is because these bits of the condition register are set from all 64 bits of the register in 64-bit mode. I don't believe it is possible to have all of EQ, LT and GT correct using only two rlwinm instructions in the mask_operand_wrap case. Causes failure of gcc.c-torture/execute/930718-1.c -- Summary: invalid rlwinm patterns Product: gcc Version: 4.0.0 Status: UNCONFIRMED Keywords: wrong-code Severity: critical Priority: P2 Component: target AssignedTo: amodra at bigpond dot net dot au ReportedBy: amodra at bigpond dot net dot au CC: gcc-bugs at gcc dot gnu dot org GCC target triplet: powerpc64-*-linux http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19147
next reply other threads:[~2004-12-24 6:25 UTC|newest] Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top 2004-12-24 6:25 amodra at bigpond dot net dot au [this message] 2004-12-24 14:38 ` [Bug target/19147] " pinskia at gcc dot gnu dot org 2004-12-24 23:00 ` cvs-commit at gcc dot gnu dot org 2004-12-24 23:15 ` cvs-commit at gcc dot gnu dot org 2004-12-24 23:17 ` cvs-commit at gcc dot gnu dot org 2004-12-24 23:22 ` amodra at bigpond dot net dot au 2005-01-26 23:22 ` cvs-commit at gcc dot gnu dot org
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