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* [Bug target/19147] New: invalid rlwinm patterns
@ 2004-12-24  6:25 amodra at bigpond dot net dot au
  2004-12-24 14:38 ` [Bug target/19147] " pinskia at gcc dot gnu dot org
                   ` (5 more replies)
  0 siblings, 6 replies; 7+ messages in thread
From: amodra at bigpond dot net dot au @ 2004-12-24  6:25 UTC (permalink / raw)
  To: gcc-bugs

andsi3_internal7 and andsi3_internal8 generate invalid LT and GT condition
codes.  This is because these bits of the condition register are set from
all 64 bits of the register in 64-bit mode.  I don't believe it is possible
to have all of EQ, LT and GT correct using only two rlwinm instructions in
the mask_operand_wrap case.

Causes failure of gcc.c-torture/execute/930718-1.c

-- 
           Summary: invalid rlwinm patterns
           Product: gcc
           Version: 4.0.0
            Status: UNCONFIRMED
          Keywords: wrong-code
          Severity: critical
          Priority: P2
         Component: target
        AssignedTo: amodra at bigpond dot net dot au
        ReportedBy: amodra at bigpond dot net dot au
                CC: gcc-bugs at gcc dot gnu dot org
GCC target triplet: powerpc64-*-linux


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19147


^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2005-01-26 23:22 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2004-12-24  6:25 [Bug target/19147] New: invalid rlwinm patterns amodra at bigpond dot net dot au
2004-12-24 14:38 ` [Bug target/19147] " pinskia at gcc dot gnu dot org
2004-12-24 23:00 ` cvs-commit at gcc dot gnu dot org
2004-12-24 23:15 ` cvs-commit at gcc dot gnu dot org
2004-12-24 23:17 ` cvs-commit at gcc dot gnu dot org
2004-12-24 23:22 ` amodra at bigpond dot net dot au
2005-01-26 23:22 ` cvs-commit at gcc dot gnu dot org

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