[Bug target/19240] [4.0 Regression] runtime performance regression in floating point heavy code, x86/SSE

["uros at kss-loka dot si" <gcc-bugzilla@gcc.gnu.org>]

------- Additional Comments From uros at kss-loka dot si  2005-01-03 16:27 -------
Ah, I see the problem. Combine pass is producing reverse div/sub patterns, where
the first operand is a memory_operand and the second is a register.
Unfortunatelly, sse patterns doesn't provide reversed patterns:

(define_insn "*fop_sf_1_sse"
  [(set (match_operand:SF 0 "register_operand" "=x")
	(match_operator:SF 3 "binary_fp_operator"
			[(match_operand:SF 1 "register_operand" "0")
			 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
...

(define_insn "*fop_sf_1_i387"
  [(set (match_operand:SF 0 "register_operand" "=f,f")
	(match_operator:SF 3 "binary_fp_operator"
			[(match_operand:SF 1 "nonimmediate_operand" "0,fm")
			 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]


SSE pattern isn't matched when first operand is memory operand and so it doesn't
shadow the 387 pattern. I think that fop_{s,d}f_1_i387 needs additional
constraint to hide them for TARGET_SSE. Perhaps:

&& !(TARGET_SSE && GET_CODE (operands[1]) == MEM)

and similar for DFmode.

-- 
           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
     Ever Confirmed|                            |1
   Last reconfirmed|0000-00-00 00:00:00         |2005-01-03 16:27:34
               date|                            |


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19240