From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 2935 invoked by alias); 27 Jun 2005 11:50:06 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org Received: (qmail 2927 invoked by uid 48); 27 Jun 2005 11:50:03 -0000 Date: Mon, 27 Jun 2005 11:50:00 -0000 Message-ID: <20050627115003.2926.qmail@sourceware.org> From: "bruno at clisp dot org" To: gcc-bugs@gcc.gnu.org In-Reply-To: <20020506130600.6585.bruno@clisp.org> References: <20020506130600.6585.bruno@clisp.org> Reply-To: gcc-bugzilla@gcc.gnu.org Subject: [Bug rtl-optimization/6585] Redundant store/load instruction pairs on ix86 X-Bugzilla-Reason: CC X-SW-Source: 2005-06/txt/msg03208.txt.bz2 List-Id: ------- Additional Comments From bruno at clisp dot org 2005-06-27 11:50 ------- Indeed, the result is much better now, nearly optimal. As you say, the only further optimization possible is that a better register allocation could get rid of the movl %edx, %esi and movl %ebx, %edi instructions. -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=6585