[Bug target/19161] No emms or femms emitted between MMX and FP instructions

["rth at gcc dot gnu dot org" <gcc-bugzilla@gcc.gnu.org>]

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------- Additional Comments From rth at gcc dot gnu dot org  2005-08-23 20:48 -------
So, I fixed another case in which we could die in create_pre_exit having
to do with complex return values.  But past that, there are failures that
are completely within optimize_mode_switching, e.g. execute/20050604-1.c.

$ ./cc1 -m32 -march=pentium4 z.c
 foo
z.c: In function ‘foo’:
z.c:28: error: unable to find a register to spill in class ‘MMX_REGS’
z.c:28: error: this is the insn:
(insn 14 63 15 2 (set (reg:V4HI 61 [ D.1620 ])
        (mem/s/j:V4HI (symbol_ref:SI ("u") <var_decl 0x2aaaadaff160 u>)
                      [0 u.v+0 S8 A64])) 994 {*movv4hi_internal} (nil)
    (nil))

The problem is that we have a CFG like
     +--+
     v  |
  1->2->3->4
and we place the efpu insn in block 2, but the emms insn in block 4.

Aside from being Less Than Ideal, this results in BOTH mmx and fpu
registers live around the loop, which means we can't allocate anything.

Uros, you should bootstrap i386 with --with-arch=foo, where foo is 
whatever machine you have that supports at least mmx.  Otherwise, you're
not actually testing this new code on i386 except for the few test
cases that force an -march or -mmx option.

I'll keep looking at it for a bit to see if its something simple, but
we're not going to overhaul optimize_mode_switching for 4.1 if it's
something complicated.

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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19161