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From: "ian at airs dot com" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug middle-end/24929] long long shift/mask operations should be better optimized Date: Thu, 02 Feb 2006 18:14:00 -0000 [thread overview] Message-ID: <20060202181429.1397.qmail@sourceware.org> (raw) In-Reply-To: <bug-24929-11148@http.gcc.gnu.org/bugzilla/> ------- Comment #2 from ian at airs dot com 2006-02-02 18:14 ------- With an updated version of RTH's subreg lowering pass, I get this instruction sequence: f: movl 16(%esp), %eax movl 4(%esp), %edx movl 8(%esp), %ecx shrl $16, %eax andl $255, %eax shldl $8, %edx, %ecx sall $8, %edx orl %edx, %eax movl %ecx, %edx ret This is one instruction shorter than the icc sequence, due to the use of shldl. It could be improved by switching the roles of %ecx and %edx to avoid the final move, although that is complex to implement give the way the register allocator currently handles pseudo-registers larger than word mode. -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=24929
next prev parent reply other threads:[~2006-02-02 18:14 UTC|newest] Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top 2005-11-18 2:30 [Bug middle-end/24929] New: " tkho at ucla dot edu 2005-11-18 2:35 ` [Bug middle-end/24929] " tkho at ucla dot edu 2006-02-02 18:14 ` ian at airs dot com [this message] 2006-02-02 18:16 ` pinskia at gcc dot gnu dot org 2006-06-27 7:39 ` ian at airs dot com 2006-06-27 13:02 ` uros at kss-loka dot si 2006-09-20 22:20 ` steven at gcc dot gnu dot org 2009-06-04 18:18 ` aldot at gcc dot gnu dot org [not found] <bug-24929-4@http.gcc.gnu.org/bugzilla/> 2021-08-29 22:39 ` pinskia at gcc dot gnu.org
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