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* [Bug c/28325] New: -fno-delayed-branch does not seem to work with the MIPS branch instructions
@ 2006-07-09 14:39 ska at bth dot se
2006-07-10 16:27 ` [Bug middle-end/28325] " ian at airs dot com
0 siblings, 1 reply; 2+ messages in thread
From: ska at bth dot se @ 2006-07-09 14:39 UTC (permalink / raw)
To: gcc-bugs
I'm working on a binary translator that translates MIPS binaries into Java
bytecode (http://spel.bth.se/index.php/Cibyl) with the goal of "recompiling" C
programs to run on J2ME. To simplify things, I use compile programs for a
subset of the MIPS1 instruction set, and ideally I would like to get rid of
delayed instructions.
So, I used the -fno-delayed-branch instruction when compiling. The GCC version
is
mips-linux-gcc (GCC) 3.4.4 20050314 (prerelease) (Debian 3.4.3-13)
(an emdebian.org binary), and the command line i used is
mips-linux-gcc -Wall -mips1 -fno-delayed-branch -O2 -fno-pic -mno-abicalls
-I/home/ska/projects/private/games/mophun/cibyl/trunk//include -O2 -c main.c
-o main.o
For the code below,
#define _syscall1(type,name,atype,a) \
type name(atype a) \
{ \
register unsigned long __a0 asm("$4") = (unsigned long) a; \
register unsigned long __v0 asm("$2"); \
\
__asm__ volatile ( \
".set\tnoreorder\n\t" \
"li\t$2, %2\t\t\t# " #name "\n\t" \
"syscall\n\t" \
".set\treorder" \
: "=&r" (__v0) \
: "r" (__a0), "i" (__NR_##name) \
); \
\
return (type) __v0; \
}
#define __NR_exit 0
static inline _syscall1(void,exit , int, code );
int tst(int *argv)
{
int x;
for (x = 0; x < 24; x++)
exit(argv[x]);
return 0;
}
I get instructions in the delay slots of bgez and jr:
00000000 <tst>:
0: 00801821 move v1,a0
4: 24050017 li a1,23
8: 8c640000 lw a0,0(v1)
c: 24020000 li v0,0
10: 0000000c syscall
14: 24a5ffff addiu a1,a1,-1
18: 04a1fffb bgez a1,8 <tst+0x8>
1c: 24630004 addiu v1,v1,4
20: 03e00008 jr ra
24: 00001021 move v0,zero
...
Which is not what I had expected. If i replace the "syscall" exit with a
function call instead, I get the expected behavior:
00000000 <exit3>:
0: 08000000 j 0 <exit3>
4: 00000000 nop
00000008 <tst>:
8: 27bdffe0 addiu sp,sp,-32
c: afb10014 sw s1,20(sp)
10: afb00010 sw s0,16(sp)
14: afbf0018 sw ra,24(sp)
18: 00808021 move s0,a0
1c: 24110017 li s1,23
20: 8e040000 lw a0,0(s0)
24: 2631ffff addiu s1,s1,-1
28: 0c000000 jal 0 <exit3>
2c: 00000000 nop
30: 26100004 addiu s0,s0,4
34: 0621fffa bgez s1,20 <tst+0x18>
38: 00000000 nop
3c: 8fbf0018 lw ra,24(sp)
40: 8fb10014 lw s1,20(sp)
44: 8fb00010 lw s0,16(sp)
48: 00001021 move v0,zero
4c: 27bd0020 addiu sp,sp,32
50: 03e00008 jr ra
54: 00000000 nop
...
--
Summary: -fno-delayed-branch does not seem to work with the MIPS
branch instructions
Product: gcc
Version: 3.4.3
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
AssignedTo: unassigned at gcc dot gnu dot org
ReportedBy: ska at bth dot se
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=28325
^ permalink raw reply [flat|nested] 2+ messages in thread
* [Bug middle-end/28325] -fno-delayed-branch does not seem to work with the MIPS branch instructions
2006-07-09 14:39 [Bug c/28325] New: -fno-delayed-branch does not seem to work with the MIPS branch instructions ska at bth dot se
@ 2006-07-10 16:27 ` ian at airs dot com
0 siblings, 0 replies; 2+ messages in thread
From: ian at airs dot com @ 2006-07-10 16:27 UTC (permalink / raw)
To: gcc-bugs
------- Comment #1 from ian at airs dot com 2006-07-10 16:27 -------
This is not a bug in the compiler. The ".set reorder" directive tells the
assembler that it should reorder instructions into branch delay slots when
possible. The compiler just copies the ".set reorder" directly from the asm
statement. Both the compiler and the assembler are acting as expected.
You should rewrite your asm statement to not use .set reorder. Do this
instead:
.set push
.set noreorder
...
.set pop
--
ian at airs dot com changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |RESOLVED
Resolution| |INVALID
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=28325
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2006-07-09 14:39 [Bug c/28325] New: -fno-delayed-branch does not seem to work with the MIPS branch instructions ska at bth dot se
2006-07-10 16:27 ` [Bug middle-end/28325] " ian at airs dot com
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