From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 27479 invoked by alias); 8 Nov 2006 20:03:13 -0000 Received: (qmail 27433 invoked by uid 48); 8 Nov 2006 20:03:02 -0000 Date: Wed, 08 Nov 2006 20:03:00 -0000 Message-ID: <20061108200302.27432.qmail@sourceware.org> X-Bugzilla-Reason: CC References: Subject: [Bug inline-asm/11203] source doesn't compile with -O0 but they compile with -O3 In-Reply-To: Reply-To: gcc-bugzilla@gcc.gnu.org To: gcc-bugs@gcc.gnu.org From: "xyzzy at speakeasy dot org" Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org X-SW-Source: 2006-11/txt/msg00677.txt.bz2 List-Id: ------- Comment #36 from xyzzy at speakeasy dot org 2006-11-08 20:03 ------- (In reply to comment #21) > asm volatile("" > : "=m" (*(unsigned int*)(src + 0*stride)), > "=m" (*(unsigned int*)(src + 1*stride)), > "=m" (*(unsigned int*)(src + 2*stride)), > "=m" (*(unsigned int*)(src + 3*stride)), > "=m" (*(unsigned int*)(src + 4*stride)), > "=m" (*(unsigned int*)(src + 5*stride)), > "=m" (*(unsigned int*)(src + 6*stride)), > "=m" (*(unsigned int*)(src + 7*stride)) > ); (In reply to comment #26) > it might also happen that in some intentionally overconstrained cases it ends up > searching the whole 5040 possible assignments of 7 registers onto 7 non memory > operands but still it wont fail The example Martin gave has *8* operands. You can try every possible direct mapping of those 8 addresses to just 7 registers, but they will obviously all fail. Except with ia32 addressing modes it _can_ be done, and with only 4 registers. reg1 = src, reg2 = stride, reg3 = src+stride*3, reg4 = src+stride*6 Then the 8 memory operands are: (reg1), (reg1,reg2,1), (reg1,reg2,2), (reg3), (reg1,reg2,4), (reg3,reg2,2), (reg4), (reg3,reg2,4) When one considers all the addressing modes, there are not just 7 possible registers, but (I think) 261 possible addresses. There are not just 5040 possibilities as Michael said, but over 76 x 10^15 possible ways of assigning these addresses to 7 operands! Then each register can be loaded not just with an address but with some sub-expression too, like how I loaded reg2 with stride. Even for ia32, which makes up for its limited number of registers with complex addressing modes, finding a register allocation that satisfies an asm statement is not something that can always be done in reasonable time. If the number of operands <= number of available registers it should be able to (but gcc doesn't) always find an allocation (_an_ allocation, not the best allocation). -- xyzzy at speakeasy dot org changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |xyzzy at speakeasy dot org http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11203