[Bug c/32961] New: GCC 4.2 has different requirements for x86 shift xmm intrinsics

[Bug c/32961] New: GCC 4.2 has different requirements for x86 shift xmm intrinsics

[mikelikespie at gmail dot com]

I have some code that uses _mm_slli_epi32 intrinsics and some other shift ones.
 This code compiles fine in GCC 4.1/4.0 and ICC 9.1.

I tried compiling it with GCC 4.2 and I get the error
testt.c:4: error: shift must be an immediate

_mm_slli_epi32 is defined as:
__m128i _mm_slli_epi32 (__m128i m, int  count)

Unfortunately, it seems like GCC 4.2 is requiring count to be an immediate.  If
an immediate were intended to be required I believe it would be named "int imm"
instead of "int count" like how _mm_slli_si128 is defined.


Here's a test case that compiles with ICC 9.1, GCC 4.0, and GCC 4.1, but not
GCC 4.2:

#include <xmmintrin.h>
void a( int n ) {
        __m128i a;
        a = _mm_slli_epi32( a, n );
}


I've also tried different flags, including both -m32 and -m64 to see if it was
an issue with that.  Nothing fixed it.


-- 
           Summary: GCC 4.2 has different requirements for x86 shift xmm
                    intrinsics
           Product: gcc
           Version: 4.2.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
        AssignedTo: unassigned at gcc dot gnu dot org
        ReportedBy: mikelikespie at gmail dot com


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=32961

[Bug c/32961] GCC 4.2 has different requirements for x86 shift xmm intrinsics

[mikelikespie at gmail dot com]

------- Comment #1 from mikelikespie at gmail dot com  2007-08-01 18:50 -------
I forgot to mention, I'm running the latest gentoo with amd64, and gcc (GCC)
4.2.0 (Gentoo 4.2.0 p1.4).


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=32961

[Bug target/32961] GCC 4.2 has different requirements for x86 shift xmm intrinsics

[mrs at apple dot com]

------- Comment #2 from mrs at apple dot com  2007-10-16 19:29 -------
I can confirm the bug and that Intel's documentation does not have a immediate
restriction on any of the epi functions.


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=32961

[Bug target/32961] [4.2/4.3 Regression]: Gcc has different requirements for x86 shift xmm intrinsics

[hjl at lucon dot org]

------- Comment #3 from hjl at lucon dot org  2007-10-16 20:02 -------
pslld[wdq] takes an xmm register as shift count. It is a bug in gcc.


-- 

hjl at lucon dot org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
     Ever Confirmed|0                           |1
   Last reconfirmed|0000-00-00 00:00:00         |2007-10-16 20:02:50
               date|                            |
            Summary|GCC 4.2 has different       |[4.2/4.3 Regression]: Gcc
                   |requirements for x86 shift  |has different requirements
                   |xmm intrinsics              |for x86 shift xmm intrinsics


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=32961

[Bug target/32961] [4.2/4.3 Regression]: Gcc has different requirements for x86 shift xmm intrinsics

[ubizjak at gmail dot com]

------- Comment #4 from ubizjak at gmail dot com  2007-10-17 07:08 -------
Patch in testing.


-- 

ubizjak at gmail dot com changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         AssignedTo|unassigned at gcc dot gnu   |ubizjak at gmail dot com
                   |dot org                     |
             Status|NEW                         |ASSIGNED
   Last reconfirmed|2007-10-16 20:02:50         |2007-10-17 07:08:45
               date|                            |


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=32961

[Bug target/32961] [4.2/4.3 Regression]: Gcc has different requirements for x86 shift xmm intrinsics

[uros at gcc dot gnu dot org]

------- Comment #5 from uros at gcc dot gnu dot org  2007-10-17 08:25 -------
Subject: Bug 32961

Author: uros
Date: Wed Oct 17 08:25:15 2007
New Revision: 129403

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=129403
Log:
        PR target/32961
        * config/i386/i386.c (ix86_expand_builtin) [IX86_BUILTIN_PSLLWI128,
        IX86_BUILTIN_PSLLDI128, BUILTIN_PSLLQI128, IX86_BUILTIN_PSRAWI128,
        IX86_BUILTIN_PSRADI128, IX86_BUILTIN_PSRLWI128,
        IX86_BUILTIN_PSRLDI128, IX86_BUILTIN_PSRLQI128]: Do not require
        immediate shift value.
        config/i386/emmintrin.h (_mm_slli_epi16, _mm_slli_epi32,
        _mm_slli_epi64, _mm_srai_epi16, _mm_srai_epi32, _mm_srli_epi16,
        _mm_srli_epi32, _mm_srli_epi64): Remove 'const' from count argument.
        Remove macros for !__OPTIMIZE__ case.

testsuite/ChangeLog:

        PR target/32961
        * gcc.target/i386/pr32961.c: New testcase.
        * gcc.target/i386/sse-13.c: Remove __builtin_ia32_psllwi128,
        __builtin_ia32_psrlqi128, __builtin_ia32_psrlwi128,
        __builtin_ia32_psrldi128, __builtin_ia32_psrawi128,
        __builtin_ia32_psradi128, __builtin_ia32_psllqi128 and
        __builtin_ia32_pslldi128 defines.


Added:
    trunk/gcc/testsuite/gcc.target/i386/pr32961.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/i386/emmintrin.h
    trunk/gcc/config/i386/i386.c
    trunk/gcc/testsuite/ChangeLog
    trunk/gcc/testsuite/gcc.target/i386/sse-12.c
    trunk/gcc/testsuite/gcc.target/i386/sse-13.c
    trunk/gcc/testsuite/gcc.target/i386/sse-14.c


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=32961

[Bug target/32961] [4.2/4.3 Regression]: Gcc has different requirements for x86 shift xmm intrinsics

[geoffk at gcc dot gnu dot org]

------- Comment #6 from geoffk at gcc dot gnu dot org  2007-10-17 21:28 -------
Shouldn't you have to use

_mm_sll_epi32(s, _mm_cvtsi32_si128 (c))

instead?  Or does the 'i' in 'slli' stand for 'int' not 'immediate'?

I thought that the list of _mm_sl* intrinsics in the assembly reference guide
(Intel doc 253667,  <http://www.intel.com/design/processor/manuals/253667.pdf>,
page 4-172 and 4-173) were supposed to match up one-for-one with the
instructions forms (on page 4-170).  The assembly reference also says that
_mm_slli_epi32 generates a single instruction, as it is listed in table C-1.

On the other hand, icc's documentation,
<http://download.intel.com/support/performancetools/c/linux/v9/intref_cls.pdf>,
on page 137, says for _mm_slli_si128, 'imm must be an immediate', but doesn't
say that for _mm_slli_epi32.


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=32961

[Bug target/32961] [4.2/4.3 Regression]: Gcc has different requirements for x86 shift xmm intrinsics

[hjl at lucon dot org]

------- Comment #7 from hjl at lucon dot org  2007-10-17 21:48 -------
Icc generates:

#include <xmmintrin.h>
__m128i
foo (__m128i a, int n )
{
  a = _mm_slli_epi32( a, n );
  return a;
}
[hjl@gnu-6 tmp]$ /opt/intel/cce/10.0/bin/icc -c x.c
[hjl@gnu-6 tmp]$ objdump -d x.o

x.o:     file format elf64-x86-64

Disassembly of section .text:

0000000000000000 <foo>:
   0:   66 0f 6e cf             movd   %edi,%xmm1
   4:   66 0f f2 c1             pslld  %xmm1,%xmm0
   8:   c3                      retq   
   9:   90                      nop    
   a:   90                      nop    
   b:   90                      nop    
[hjl@gnu-6 tmp]$ 

BTW, _mm_slli_si128 maps to "pslldq" and it only takes imm as shift count.


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=32961

[Bug target/32961] [4.2/4.3 Regression]: Gcc has different requirements for x86 shift xmm intrinsics

[geoffk at gcc dot gnu dot org]

------- Comment #8 from geoffk at gcc dot gnu dot org  2007-10-18 04:53 -------
(In reply to comment #7)
> Icc generates:
>    0:   66 0f 6e cf             movd   %edi,%xmm1
>    4:   66 0f f2 c1             pslld  %xmm1,%xmm0

Right, that's what icc's documentation would suggest.  But that documentation
seems inconsistent with the assembly reference guide.  It may be that the
assembly reference guide is the one that's wrong, or that icc intentionally
extends it.


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=32961

[Bug target/32961] [4.2/4.3 Regression]: Gcc has different requirements for x86 shift xmm intrinsics

[ubizjak at gmail dot com]

------- Comment #9 from ubizjak at gmail dot com  2007-10-18 06:33 -------
(In reply to comment #8)

> > Icc generates:
> >    0:   66 0f 6e cf             movd   %edi,%xmm1
> >    4:   66 0f f2 c1             pslld  %xmm1,%xmm0
> 
> Right, that's what icc's documentation would suggest.  But that documentation
> seems inconsistent with the assembly reference guide.  It may be that the
> assembly reference guide is the one that's wrong, or that icc intentionally
> extends it.

I think we should follow icc example, because there is realy no problem to
support immediates and non-immediates for these insns. Supporting only
immediates looks like forced limitation to me, even if it is required.


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=32961

[Bug target/32961] [4.2/4.3 Regression]: Gcc has different requirements for x86 shift xmm intrinsics

[uros at gcc dot gnu dot org]

------- Comment #10 from uros at gcc dot gnu dot org  2007-10-18 09:12 -------
Subject: Bug 32961

Author: uros
Date: Thu Oct 18 09:12:30 2007
New Revision: 129433

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=129433
Log:
        PR target/32961
        * config/i386/i386.c (ix86_expand_builtin) [IX86_BUILTIN_PSLLWI128,
        IX86_BUILTIN_PSLLDI128, BUILTIN_PSLLQI128, IX86_BUILTIN_PSRAWI128,
        IX86_BUILTIN_PSRADI128, IX86_BUILTIN_PSRLWI128,
        IX86_BUILTIN_PSRLDI128, IX86_BUILTIN_PSRLQI128]: Do not require
        immediate shift value.
        * config/i386/emmintrin.h (_mm_slli_epi16, _mm_slli_epi32,
        _mm_slli_epi64, _mm_srai_epi16, _mm_srai_epi32, _mm_srli_epi16,
        _mm_srli_epi32, _mm_srli_epi64):  Enable disabled functions and
        remove equivalent macro definitions.

testsuite/ChangeLog:

        PR target/32961
        * gcc.target/i386/pr32961.c: New testcase.


Added:
    branches/gcc-4_2-branch/gcc/testsuite/gcc.target/i386/pr32961.c
Modified:
    branches/gcc-4_2-branch/gcc/ChangeLog
    branches/gcc-4_2-branch/gcc/config/i386/emmintrin.h
    branches/gcc-4_2-branch/gcc/config/i386/i386.c
    branches/gcc-4_2-branch/gcc/testsuite/ChangeLog


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=32961

[Bug target/32961] [4.2/4.3 Regression]: Gcc has different requirements for x86 shift xmm intrinsics

[ubizjak at gmail dot com]

------- Comment #11 from ubizjak at gmail dot com  2007-10-18 09:14 -------
Fixed for 4.2.3 and 4.3.0.


-- 

ubizjak at gmail dot com changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
         Resolution|                            |FIXED
   Target Milestone|---                         |4.2.3


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=32961

[Bug target/32961] [4.2/4.3 Regression]: Gcc has different requirements for x86 shift xmm intrinsics

[hjl at lucon dot org]

------- Comment #12 from hjl at lucon dot org  2007-10-18 13:44 -------
(In reply to comment #8)
> (In reply to comment #7)
> > Icc generates:
> >    0:   66 0f 6e cf             movd   %edi,%xmm1
> >    4:   66 0f f2 c1             pslld  %xmm1,%xmm0
> 
> Right, that's what icc's documentation would suggest.  But that documentation
> seems inconsistent with the assembly reference guide.  It may be that the
> assembly reference guide is the one that's wrong, or that icc intentionally
> extends it.
> 

There is nothing wrong with IA32 SDM. One intrinsic does map to one
assembly instruction, but not necessarily the same instruction every
time. Another example is _mm_cmpistrm and its friends.


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=32961