[Bug target/34091] [4.2/4.3 Regression] ICE in reload_cse_simplify_operands, at postreload.c:392

["dave at hiauly1 dot hia dot nrc dot ca" <gcc-bugzilla@gcc.gnu.org>]

------- Comment #10 from dave at hiauly1 dot hia dot nrc dot ca  2007-11-24 21:31 -------
Subject: Re:  [4.2/4.3 Regression] ICE in reload_cse_simplify_operands, at
postreload.c:392

>    We need a temporary when loading/storing a HImode/QImode value
>    between memory and the FPU registers.  This can happen when combine puts
>    a paradoxical subreg in a float/fix conversion insn.

This looks like an alternative solution to the HImode/QImode problem,
although the SECONDARY_INPUT_RELOAD_CLASS and SECONDARY_OUTPUT_RELOAD_CLASS
macros are now obsolete.  Guess the same could be done with
TARGET_SECONDARY_RELOAD.

Is there a reason why you want to load/store HImode/QImode values in
the FPU registers on sparc?  On the pa, there aren't any insns that
operate on them.  So, the only reason we supported this was because
these modes are tied to SImode and DImode.  Not supporting FPU loads
and stores of HImode/QImode values allowed me to eliminates some
duplication of patterns.

I haven't seen the paradoxical subreg in a float/fix conversion
insns with the current patch.  I did see this in some of the first
versions of pa_cannot_change_mode_class.  I think I eliminated
this problem by prevent mode changes in the FP registers:

  if (MAYBE_FP_REG_CLASS_P (class))
      return true;

Due you think this problem is latent?

I stopped using secondary memory on the 32-bit targets because
FPU loads and stores only support 5-bit immediates.  Because of this,
the port was using SECONDARY_MEMORY_NEEDED_RTX and a free stack
slot in the frame marker of the caller.  However, this failed in
the rare case when a const function got placed between the load
and store.

I moved the SECONDARY_MEMORY_NEEDED define as I saw some code
while debugging that wasn't optimised away on the 32-bit port.

Dave


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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34091