From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 14360 invoked by alias); 23 Jan 2008 02:51:02 -0000 Received: (qmail 14100 invoked by uid 48); 23 Jan 2008 02:50:14 -0000 Date: Wed, 23 Jan 2008 03:05:00 -0000 Message-ID: <20080123025014.14099.qmail@sourceware.org> X-Bugzilla-Reason: CC References: Subject: [Bug target/34932] [avr] ICE in reload In-Reply-To: Reply-To: gcc-bugzilla@gcc.gnu.org To: gcc-bugs@gcc.gnu.org From: "hutchinsonandy at aim dot com" Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org X-SW-Source: 2008-01/txt/msg02681.txt.bz2 ------- Comment #3 from hutchinsonandy at aim dot com 2008-01-23 02:50 ------- The pattern requires operand 1 to be same register as operand 0 Operands 1 & 2 share 2 subregs of same Himode register R22 But should have been solvable without any problem, since HI24 is just right! QI:21 -> QI:24 HI24 = Zex:QI24 + ZexQI22 voila! QI22 could have been in top half of HI24. So this also works HI:22 - > HI:22 HI:24 = Zex:QI24 + ZexQI24 -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34932