[Bug target/35189] New: -mno-sse4.2 turns off SSE4a

[Bug target/35189] New: -mno-sse4.2 turns off SSE4a

[hjl dot tools at gmail dot com]

[hjl@gnu-6 tmp]$ cat y.c
#include <stdio.h>

int
main ()
{
#ifdef __SSE__
  printf ("SSE\n");
#endif
#ifdef __SSE2__
  printf ("SSE2\n");
#endif
#ifdef __SSE3__
  printf ("SSE3\n");
#endif
#ifdef __SSSE3__
  printf ("SSSE3\n");
#endif
#ifdef __SSE4_1__
  printf ("SSE4.1\n");
#endif
#ifdef __SSE4_2__
  printf ("SSE4.2\n");
#endif
#ifdef __SSE4A__
  printf ("SSE4A\n");
#endif
}
[hjl@gnu-6 tmp]$ /usr/gcc-4.3/bin/gcc -march=core2 -mno-sse4.2 y.c && ./a.out
SSE
SSE2
SSE3
SSSE3
[hjl@gnu-6 tmp]$ /usr/gcc-4.3/bin/gcc -march=amdfam10 -mno-sse4.2 y.c &&
./a.out 
SSE
SSE2
SSE3
[hjl@gnu-6 tmp]$ /usr/gcc-4.3/bin/gcc -march=amdfam10 y.c && ./a.out
SSE
SSE2
SSE3
SSE4A
[hjl@gnu-6 tmp]$


-- 
           Summary: -mno-sse4.2 turns off SSE4a
           Product: gcc
           Version: 4.3.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
        AssignedTo: unassigned at gcc dot gnu dot org
        ReportedBy: hjl dot tools at gmail dot com
GCC target triplet: i686-pc-linux-gnu


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35189

[Bug target/35189] -mno-sse4.2 turns off SSE4a

[pinskia at gcc dot gnu dot org]

------- Comment #1 from pinskia at gcc dot gnu dot org  2008-02-13 23:49 -------
#define OPTION_MASK_ISA_SSE4_2_UNSET OPTION_MASK_ISA_SSE4A


I don't see this as a bug, if the AMD processors don't have 4.2, they will
never have 4a.


-- 

pinskia at gcc dot gnu dot org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|                            |INVALID


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35189

[Bug target/35189] -mno-sse4.2 turns off SSE4a

[michael dot meissner at amd dot com]

------- Comment #2 from michael dot meissner at amd dot com  2008-02-13 23:55 -------
Umm, SSE4A is completely different from SSE4/SSE4.1/SSE4.2.  SSE4A are the
instructions added with AMD's Barcelona machine, while SSE4.1 is the
instructions added with the current generation of Intel machines (Penryn if
memory serves), and SSE4.2 will be the instructions in the next Intel release. 
The whole naming scheme is unfortunate, especially SSSE3 and SSE4A. 


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35189

[Bug target/35189] -mno-sse4.2 turns off SSE4a

[hjl dot tools at gmail dot com]

------- Comment #3 from hjl dot tools at gmail dot com  2008-02-14 00:11 -------
-mno-sse4.1 and -mno-sse4.2 shouldn't turn off SSE4A.
-mno-sse3/-mno-sse2/-mno-sse should turn off SSE4A. But
I am not sure about -mno-ssse3.


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35189

[Bug target/35189] -mno-sse4.2 turns off SSE4a

[michael dot meissner at amd dot com]

------- Comment #4 from michael dot meissner at amd dot com  2008-02-14 00:20 -------
In terms of shipping systems, no AMD system supports SSSE3 right now.  As I
understand it, the SSSE3 instructions were inbetween SSE3 and SSE4.1 on Intel
systems, so -mno-sse3 should turn off SSSE3, but -mno-sse4a should not turn off
SSSE3.  Current shipping AMD systems do support SSE3.


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35189

[Bug target/35189] -mno-sse4.2 turns off SSE4a

[hjl dot tools at gmail dot com]

------- Comment #5 from hjl dot tools at gmail dot com  2008-02-14 01:44 -------
A patch is posted at

http://gcc.gnu.org/ml/gcc-patches/2008-02/msg00483.html


-- 

hjl dot tools at gmail dot com changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|RESOLVED                    |UNCONFIRMED
         Resolution|INVALID                     |


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35189

[Bug target/35189] -mno-sse4.2 turns off SSE4a

[hjl at gcc dot gnu dot org]

------- Comment #6 from hjl at gcc dot gnu dot org  2008-02-19 01:21 -------
Subject: Bug 35189

Author: hjl
Date: Tue Feb 19 01:21:03 2008
New Revision: 132403

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=132403
Log:
gcc/

2008-02-18  H.J. Lu  <hongjiu.lu@intel.com>

        PR target/35189
        * config/i386/i386.c (OPTION_MASK_ISA_MMX_SET): New.
        (OPTION_MASK_ISA_3DNOW_SET): Likewise.
        (OPTION_MASK_ISA_SSE_SET): Likewise.
        (OPTION_MASK_ISA_SSE2_SET): Likewise.
        (OPTION_MASK_ISA_SSE3_SET): Likewise.
        (OPTION_MASK_ISA_SSSE3_SET): Likewise.
        (OPTION_MASK_ISA_SSE4_1_SET): Likewise.
        (OPTION_MASK_ISA_SSE4_2_SET): Likewise.
        (OPTION_MASK_ISA_SSE4_SET): Likewise.
        (OPTION_MASK_ISA_SSE4A_SET): Likewise.
        (OPTION_MASK_ISA_SSE5_SET): Likewise.
        (OPTION_MASK_ISA_3DNOW_A_UNSET): Likewise.
        (OPTION_MASK_ISA_MMX_UNSET): Updated.
        (OPTION_MASK_ISA_3DNOW_UNSET): Updated.
        (OPTION_MASK_ISA_SSE_UNSET): Likewise.
        (OPTION_MASK_ISA_SSE3_UNSET): Likewise.
        (OPTION_MASK_ISA_SSSE3_UNSET): Likewise.
        (OPTION_MASK_ISA_SSE4_1_UNSET): Likewise.
        (OPTION_MASK_ISA_SSE4_2_UNSET): Likewise.
        (OPTION_MASK_ISA_SSE4A_UNSET): Likewise.
        (OPTION_MASK_ISA_SSE5_UNSET): Likewise.
        (OPTION_MASK_ISA_SSE4): Removed.
        (ix86_handle_option): Turn on bits in ix86_isa_flags and
        ix86_isa_flags_explicit with OPTION_MASK_ISA_XXX_SET for
        -mXXX.
        (override_options): Don't turn on implied SSE/MMX bits in
        ix86_isa_flags.

gcc/testsuite/

2008-02-18  H.J. Lu  <hongjiu.lu@intel.com>

        PR target/35189
        * gcc.target/i386/isa-1.c: New.
        * gcc.target/i386/isa-2.c: Likewise.
        * gcc.target/i386/isa-3.c: Likewise.
        * gcc.target/i386/isa-4.c: Likewise.
        * gcc.target/i386/isa-5.c: Likewise.
        * gcc.target/i386/isa-6.c: Likewise.
        * gcc.target/i386/isa-7.c: Likewise.
        * gcc.target/i386/isa-8.c: Likewise.
        * gcc.target/i386/isa-9.c: Likewise.
        * gcc.target/i386/isa-10.c: Likewise.
        * gcc.target/i386/isa-11.c: Likewise.
        * gcc.target/i386/isa-12.c: Likewise.
        * gcc.target/i386/isa-13.c: Likewise.
        * gcc.target/i386/isa-14.c: Likewise.

Added:
    trunk/gcc/testsuite/gcc.target/i386/isa-1.c
    trunk/gcc/testsuite/gcc.target/i386/isa-10.c
    trunk/gcc/testsuite/gcc.target/i386/isa-11.c
    trunk/gcc/testsuite/gcc.target/i386/isa-12.c
    trunk/gcc/testsuite/gcc.target/i386/isa-13.c
    trunk/gcc/testsuite/gcc.target/i386/isa-14.c
    trunk/gcc/testsuite/gcc.target/i386/isa-2.c
    trunk/gcc/testsuite/gcc.target/i386/isa-3.c
    trunk/gcc/testsuite/gcc.target/i386/isa-4.c
    trunk/gcc/testsuite/gcc.target/i386/isa-5.c
    trunk/gcc/testsuite/gcc.target/i386/isa-6.c
    trunk/gcc/testsuite/gcc.target/i386/isa-7.c
    trunk/gcc/testsuite/gcc.target/i386/isa-8.c
    trunk/gcc/testsuite/gcc.target/i386/isa-9.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/i386/i386.c
    trunk/gcc/testsuite/ChangeLog


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35189

[Bug target/35189] -mno-sse4.2 turns off SSE4a

[hjl at gcc dot gnu dot org]

------- Comment #7 from hjl at gcc dot gnu dot org  2008-03-07 00:08 -------
Subject: Bug 35189

Author: hjl
Date: Fri Mar  7 00:07:36 2008
New Revision: 132994

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=132994
Log:
gcc/

2008-03-06  H.J. Lu  <hongjiu.lu@intel.com>

        Backport from mainline:
        2008-02-18  H.J. Lu  <hongjiu.lu@intel.com>

        PR target/35189
        * config/i386/i386.c (OPTION_MASK_ISA_MMX_SET): New.
        (OPTION_MASK_ISA_3DNOW_SET): Likewise.
        (OPTION_MASK_ISA_SSE_SET): Likewise.
        (OPTION_MASK_ISA_SSE2_SET): Likewise.
        (OPTION_MASK_ISA_SSE3_SET): Likewise.
        (OPTION_MASK_ISA_SSSE3_SET): Likewise.
        (OPTION_MASK_ISA_SSE4_1_SET): Likewise.
        (OPTION_MASK_ISA_SSE4_2_SET): Likewise.
        (OPTION_MASK_ISA_SSE4_SET): Likewise.
        (OPTION_MASK_ISA_SSE4A_SET): Likewise.
        (OPTION_MASK_ISA_SSE5_SET): Likewise.
        (OPTION_MASK_ISA_3DNOW_A_UNSET): Likewise.
        (OPTION_MASK_ISA_MMX_UNSET): Updated.
        (OPTION_MASK_ISA_3DNOW_UNSET): Updated.
        (OPTION_MASK_ISA_SSE_UNSET): Likewise.
        (OPTION_MASK_ISA_SSE3_UNSET): Likewise.
        (OPTION_MASK_ISA_SSSE3_UNSET): Likewise.
        (OPTION_MASK_ISA_SSE4_1_UNSET): Likewise.
        (OPTION_MASK_ISA_SSE4_2_UNSET): Likewise.
        (OPTION_MASK_ISA_SSE4A_UNSET): Likewise.
        (OPTION_MASK_ISA_SSE5_UNSET): Likewise.
        (OPTION_MASK_ISA_SSE4): Removed.
        (ix86_handle_option): Turn on bits in ix86_isa_flags and
        ix86_isa_flags_explicit with OPTION_MASK_ISA_XXX_SET for
        -mXXX.
        (override_options): Don't turn on implied SSE/MMX bits in
        ix86_isa_flags.

gcc/testsuite/

2008-03-06  H.J. Lu  <hongjiu.lu@intel.com>

        Backport from mainline:
        2008-02-18  H.J. Lu  <hongjiu.lu@intel.com>

        PR target/35189
        * gcc.target/i386/isa-1.c: New.
        * gcc.target/i386/isa-2.c: Likewise.
        * gcc.target/i386/isa-3.c: Likewise.
        * gcc.target/i386/isa-4.c: Likewise.
        * gcc.target/i386/isa-5.c: Likewise.
        * gcc.target/i386/isa-6.c: Likewise.
        * gcc.target/i386/isa-7.c: Likewise.
        * gcc.target/i386/isa-8.c: Likewise.
        * gcc.target/i386/isa-9.c: Likewise.
        * gcc.target/i386/isa-10.c: Likewise.
        * gcc.target/i386/isa-11.c: Likewise.
        * gcc.target/i386/isa-12.c: Likewise.
        * gcc.target/i386/isa-13.c: Likewise.
        * gcc.target/i386/isa-14.c: Likewise.

Added:
    branches/gcc-4_3-branch/gcc/testsuite/gcc.target/i386/isa-1.c
    branches/gcc-4_3-branch/gcc/testsuite/gcc.target/i386/isa-10.c
    branches/gcc-4_3-branch/gcc/testsuite/gcc.target/i386/isa-11.c
    branches/gcc-4_3-branch/gcc/testsuite/gcc.target/i386/isa-12.c
    branches/gcc-4_3-branch/gcc/testsuite/gcc.target/i386/isa-13.c
    branches/gcc-4_3-branch/gcc/testsuite/gcc.target/i386/isa-14.c
    branches/gcc-4_3-branch/gcc/testsuite/gcc.target/i386/isa-2.c
    branches/gcc-4_3-branch/gcc/testsuite/gcc.target/i386/isa-3.c
    branches/gcc-4_3-branch/gcc/testsuite/gcc.target/i386/isa-4.c
    branches/gcc-4_3-branch/gcc/testsuite/gcc.target/i386/isa-5.c
    branches/gcc-4_3-branch/gcc/testsuite/gcc.target/i386/isa-6.c
    branches/gcc-4_3-branch/gcc/testsuite/gcc.target/i386/isa-7.c
    branches/gcc-4_3-branch/gcc/testsuite/gcc.target/i386/isa-8.c
    branches/gcc-4_3-branch/gcc/testsuite/gcc.target/i386/isa-9.c
Modified:
    branches/gcc-4_3-branch/gcc/ChangeLog
    branches/gcc-4_3-branch/gcc/config/i386/i386.c
    branches/gcc-4_3-branch/gcc/testsuite/ChangeLog


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35189

[Bug target/35189] -mno-sse4.2 turns off SSE4a

[hjl dot tools at gmail dot com]

------- Comment #8 from hjl dot tools at gmail dot com  2008-03-07 04:24 -------
Fixed.


-- 

hjl dot tools at gmail dot com changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
      Known to work|4.4.0                       |4.4.0 4.3.1
         Resolution|                            |FIXED


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35189

[Bug target/35189] -mno-sse4.2 turns off SSE4a

[ubizjak at gmail dot com]

------- Comment #9 from ubizjak at gmail dot com  2008-03-07 06:50 -------
(In reply to comment #8)
> Fixed.

Does this patch also fix PR target/35350?


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35189