From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 22847 invoked by alias); 25 Feb 2008 11:37:30 -0000 Received: (qmail 21521 invoked by uid 48); 25 Feb 2008 11:36:39 -0000 Date: Mon, 25 Feb 2008 11:37:00 -0000 Message-ID: <20080225113639.21520.qmail@sourceware.org> X-Bugzilla-Reason: CC References: Subject: [Bug middle-end/35363] Missing bit field coalscing optimization In-Reply-To: Reply-To: gcc-bugzilla@gcc.gnu.org To: gcc-bugs@gcc.gnu.org From: "rguenth at gcc dot gnu dot org" Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org X-SW-Source: 2008-02/txt/msg02631.txt.bz2 ------- Comment #1 from rguenth at gcc dot gnu dot org 2008-02-25 11:36 ------- (please make our work easier and make the initial reports Severity enhancement and add missed-optimization as a Keyword and make the report against a gcc version, preferably 4.3.0 or 4.4.0; testcases ready for inclusion into the gcc testsuite would be nice as well, as well as checking for duplicate reports yourself). This testcase actually requires one load, one and (mask out bits in the affected bitfield parts), one or and one store. The MEM_REF work might lay grounds for this to work, it makes the read-modify-write cycles explicit on the tree level and thus allows the loads and stores to be CSEd. -- rguenth at gcc dot gnu dot org changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |rguenth at gcc dot gnu dot | |org Severity|normal |enhancement Status|UNCONFIRMED |NEW Ever Confirmed|0 |1 Keywords| |missed-optimization Last reconfirmed|0000-00-00 00:00:00 |2008-02-25 11:36:39 date| | Version|unknown |4.3.0 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35363