[Bug target/11259] [avr] gcc Double 'andi' missed optimization

[Bug target/11259] [avr] gcc Double 'andi' missed optimization

[eweddington at cso dot atmel dot com]

------- Comment #7 from eweddington at cso dot atmel dot com  2007-07-25 00:04 -------
Bug still exists on 4.2.1.


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eweddington at cso dot atmel dot com changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
      Known to fail|                            |4.2.1
   Last reconfirmed|2005-12-07 04:57:01         |2007-07-25 00:04:05
               date|                            |


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11259

[Bug target/11259] [avr] gcc Double 'andi' missed optimization

[rask at gcc dot gnu dot org]

------- Comment #8 from rask at gcc dot gnu dot org  2007-11-28 22:07 -------
Created an attachment (id=14658)
 --> (http://gcc.gnu.org/bugzilla/attachment.cgi?id=14658&action=view)
example patch

This patch is an example of the suggestion in comment #6. When compiling with
-S -dp, it is clear why the code isn't optimized: "swap+andi" is one
instruction.

test:
/* prologue: function */
/* frame size = 0 */
        in r24,50-0x20           ;  6   *movqi/4        [length = 1]
        swap r24                 ;  7   lshrqi3/5       [length = 2]
        andi r24,0x0f
        andi r24,lo8(12)         ;  13  andqi3/2        [length = 1]
/* epilogue start */
        ret                      ;  26  return          [length = 1]

The patch makes two instructions out of "swap"+"andi" of which "andi" is
optimized away:

test:
/* prologue: function */
/* frame size = 0 */
        in r24,50-0x20           ;  6   *movqi/4        [length = 1]
        swap r24                 ;  7   _rotlqi3_const4 [length = 1]
        andi r24,lo8(12)         ;  14  andqi3/2        [length = 1]
/* epilogue start */
        ret                      ;  27  return          [length = 1]


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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11259

[Bug target/11259] [avr] gcc Double 'andi' missed optimization

[aesok at gcc dot gnu dot org]

------- Comment #9 from aesok at gcc dot gnu dot org  2008-08-22 21:26 -------
Subject: Bug 11259

Author: aesok
Date: Fri Aug 22 21:24:56 2008
New Revision: 139502

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=139502
Log:
        PR target/11259
        * config/avr/avr.md (UNSPEC_SWAP): New constants.
        (*swap): New insn pattern.
        (*ashlqi3): Rename from ashlqi3 insn pattern.
        (ashlqi3): New expanders.
        (*lshrqi3): Rename from lshrqi3 insn pattern.
        (lshrqi3): New expanders.       
        (ashlqi3_const4, ashlqi3_const5, ashlqi3_const6, lshrqi3_const4,
        lshrqi3_const5, lshrqi3_const6): New splitters.
        (andi, ashlqi3_l_const4, ashlqi3_l_const5, ashlqi3_l_const6,
        lshrqi3_l_const4, lshrqi3_l_const5, lshrqi3_l_const6): Define
        peephole2 patterns.

Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/avr/avr.md


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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11259

[Bug target/11259] [avr] gcc Double 'andi' missed optimization

[eric dot weddington at atmel dot com]

------- Comment #10 from eric dot weddington at atmel dot com  2008-08-22 23:06 -------
Fixed on 4.4.


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eric dot weddington at atmel dot com changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|                            |FIXED
   Target Milestone|---                         |4.4.0


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11259

[Bug target/11259] [avr] gcc Double 'andi' missed optimization

[roger at eyesopen dot com]

------- Additional Comments From roger at eyesopen dot com  2003-11-11 04:23 -------
The AVR backend defines its lshrqi3 patterns as opaque "macro" sequences,
hence the fact that "x >> 4" is implemented as a swap/rotate followed by
an and instruction is never exposed to GCC's RTL optimizers.  If it were,
the two ands would be optimized away by CSE, combine or peephole, as they
are for other targets.

As there's nothing the middle-end can do unless the AVR backend is rewritten
to use RTL expanders, I'm changing this PR's component to target/11259.


-- 
           What    |Removed                     |Added
----------------------------------------------------------------------------
          Component|optimization                |target


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11259