From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28124 invoked by alias); 11 Sep 2008 17:34:55 -0000 Received: (qmail 27724 invoked by uid 48); 11 Sep 2008 17:33:34 -0000 Date: Thu, 11 Sep 2008 17:34:00 -0000 Message-ID: <20080911173334.27723.qmail@sourceware.org> X-Bugzilla-Reason: CC References: Subject: [Bug target/37364] [4.4 Regression] IRA generates inefficient code due to missing regmove pass In-Reply-To: Reply-To: gcc-bugzilla@gcc.gnu.org To: gcc-bugs@gcc.gnu.org From: "ubizjak at gmail dot com" Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org X-SW-Source: 2008-09/txt/msg01385.txt.bz2 ------- Comment #16 from ubizjak at gmail dot com 2008-09-11 17:33 ------- (In reply to comment #15) > Uros, does your comment #11 apply also to SSE registers (Yi), which could > alleviate for PR 37437, or only to MMX (Ym)? Comment #11 is also true for Yi SSE registers (for TARGET_INTER_UNIT_MOVES targets, i.e. -march=core2). Under integer register shortage, allocator will start to allocate SSE registers, and reload will later generate various xmm->reg moves to satisfy subsequent instruction constraints. -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=37364