From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 30077 invoked by alias); 10 Nov 2008 16:13:26 -0000 Received: (qmail 18644 invoked by uid 48); 10 Nov 2008 16:12:03 -0000 Date: Mon, 10 Nov 2008 16:13:00 -0000 Message-ID: <20081110161203.18643.qmail@sourceware.org> X-Bugzilla-Reason: CC References: Subject: [Bug rtl-optimization/37948] [4.4 Regression] IRA generates slower code In-Reply-To: Reply-To: gcc-bugzilla@gcc.gnu.org To: gcc-bugs@gcc.gnu.org From: "vmakarov at redhat dot com" Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org X-SW-Source: 2008-11/txt/msg00724.txt.bz2 ------- Comment #8 from vmakarov at redhat dot com 2008-11-10 16:12 ------- H.J., thanks for finding the problem and reducing the test case. The problem could be solved by using extended register coalescing. Now IRA coalesces only move insns (-fira-coalesce). But unfortunately usage of -fira-coalesce makes worse code in general case. Register preferencing based on hard register costs works generally better in IRA. Therefore I've tried to find what is wrong with the hard register cost calculation. Why loading register from its equivalent memory location and 3 usages of the register in the loop of 36.c is cheaper than 1 def and 1 usage of another pseudo-register (that is major difference from the old register allocator). The problem is in usage GENERAL_REGS class to calculate saving from loading pseudo from the equivalent memory instead of pseudo cover class (SSE_REGS). It gives from cost 12 instead of 6 which results in wrong choice for spilling and worse code. I'll send a patch fixing this problem a bit later today. -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=37948