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References: <bug-40022-17675@http.gcc.gnu.org/bugzilla/>
Subject: [Bug middle-end/40022] [4.4/4.5 Regression] Alpine miscompilation
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------- Comment #7 from jakub at gcc dot gnu dot org  2009-05-05 10:01 -------
Introduced during tuples merge apparently (haven't bisected the tuples branch
though).
To me this looks like a phiprop bug.
In *.alias (trunk, -O2) we have:
  # BLOCK 3 freq:9100
  # PRED: 4 [91.0%]  (true,exec)
  # VUSE <.MEMD.2716_19>
  D.1614_8 = *cD.1606_1;
  cD.1606_9 = &D.1614_8->aD.1593;
  # SUCC: 4 [100.0%]  (fallthru,dfs_back,exec)

  # BLOCK 4 freq:10000
  # PRED: 2 [100.0%]  (fallthru,exec) 3 [100.0%]  (fallthru,dfs_back,exec)
  # cD.1606_1 = PHI <cD.1606_4(2), cD.1606_9(3)>
  # VUSE <.MEMD.2716_19>
  D.1614_7 = *cD.1606_1;
  if (D.1614_7 != 0B)
    goto <bb 3>;
  else
    goto <bb 5>;
  # SUCC: 3 [91.0%]  (true,exec) 5 [9.0%]  (false,exec)

  # BLOCK 5 freq:900
  # PRED: 4 [9.0%]  (false,exec)
  # .MEMD.2716_20 = VDEF <.MEMD.2716_19>
  D.1615_11 = fooD.1597 (yD.1602_10(D));
  # .MEMD.2716_21 = VDEF <.MEMD.2716_20>
  *cD.1606_1 = D.1615_11;
  goto <bb 7>;
  # SUCC: 7 [100.0%]  (fallthru,exec)

  # BLOCK 6 freq:9100
  # PRED: 7 [91.0%]  (true,exec)
  # VUSE <.MEMD.2716_21>
  D.1614_13 = *cD.1606_2;
  cD.1606_14 = &D.1614_13->aD.1593;
  # SUCC: 7 [100.0%]  (fallthru,dfs_back,exec)

  # BLOCK 7 freq:10000
  # PRED: 5 [100.0%]  (fallthru,exec) 6 [100.0%]  (fallthru,dfs_back,exec)
  # cD.1606_2 = PHI <cD.1606_1(5), cD.1606_14(6)>
  # VUSE <.MEMD.2716_21>
  D.1614_12 = *cD.1606_2;
  if (D.1614_12 != 0B)
    goto <bb 6>;
  else
    goto <bb 8>;
  # SUCC: 6 [91.0%]  (true,exec) 8 [9.0%]  (false,exec)

Note that the D.1614_12 = *cD.1606_2 read depends on the *cD.1606_1 =
D.1615_11;
store.  In phiprop we have though:

  # BLOCK 3 freq:9100
  # PRED: 4 [91.0%]  (true,exec)
  cD.1606_9 = &D.1614_8->aD.1593;
  # VUSE <.MEMD.2716_19>
  D.2745_25 = D.1614_8->aD.1593;
  # SUCC: 4 [100.0%]  (fallthru,dfs_back,exec)

  # BLOCK 4 freq:10000
  # PRED: 2 [100.0%]  (fallthru,exec) 3 [100.0%]  (fallthru,dfs_back,exec)
  # cD.1606_1 = PHI <cD.1606_4(2), cD.1606_9(3)>
  # D.1614_8 = PHI <D.2744_24(2), D.2745_25(3)>
  D.1614_7 = D.1614_8;
  if (D.1614_7 != 0B)
    goto <bb 3>;
  else
    goto <bb 5>;
  # SUCC: 3 [91.0%]  (true,exec) 5 [9.0%]  (false,exec)

  # BLOCK 5 freq:900
  # PRED: 4 [9.0%]  (false,exec)
  # .MEMD.2716_20 = VDEF <.MEMD.2716_19>
  D.1615_11 = fooD.1597 (yD.1602_10(D));
  # .MEMD.2716_21 = VDEF <.MEMD.2716_20>
  *cD.1606_1 = D.1615_11;
  goto <bb 7>;
  # SUCC: 7 [100.0%]  (fallthru,exec)

  # BLOCK 6 freq:9100
  # PRED: 7 [91.0%]  (true,exec)
  cD.1606_14 = &D.1614_13->aD.1593;
  # VUSE <.MEMD.2716_21>
  D.2746_26 = D.1614_13->aD.1593;
  # SUCC: 7 [100.0%]  (fallthru,dfs_back,exec)

  # BLOCK 7 freq:10000
  # PRED: 5 [100.0%]  (fallthru,exec) 6 [100.0%]  (fallthru,dfs_back,exec)
  # cD.1606_2 = PHI <cD.1606_1(5), cD.1606_14(6)>
  # D.1614_13 = PHI <D.1614_8(5), D.2746_26(6)>
  D.1614_12 = D.1614_13;
  if (D.1614_12 != 0B)
    goto <bb 6>;
  else
    goto <bb 8>;
  # SUCC: 6 [91.0%]  (true,exec) 8 [9.0%]  (false,exec)

Note that the D.1614_13 PHI now uses D.1614_8, which is correct *c content
only if the *cD.1606_1 = D.1615_11; store wasn't performed.  This store
obviously can change what *c contains.  Later passes then find out that
D.1614_8 must be 0 to reach BB5 and BB7, so the whole second while loop is
removed.


-- 

jakub at gcc dot gnu dot org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|[4.4 Regression] breaks     |[4.4/4.5 Regression] Alpine
                   |"reply to all" in alpine    |miscompilation


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=40022